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8XC196NP, 80C196NU USER’S MANUAL
13-24
13.5.3 8-bit Bus Timings
Figure 13-12 shows idealized 8-bit timings for the 8XC196NP. One cycle is required for an 8-bit
read or write. A 16-bit access requires two cycles. The first cycle accesses the lower byte, and the
second cycle accesses the upper byte. Except for requiring an extra cycle to write the bytes sep-
arately, the timings are the same as on the 16-bit bus, and the comparison between the multiplexed
and demultiplexed cases is also the same. The demultiplexed bus can accommodate slower mem-
ory devices than the multiplexed bus can.