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Glossary-6
8XC196NP, 80C196NU USER’S MANUAL
PSW Processor status word. The high byte of the PSW is
the status byte, which contains one bit that globally
enables or disables servicing of all maskable
interrupts, one bit that enables or disables the PTS,
and six Boolean flags that reflect the state of the
current program. The low byte of the PSW is the
INT_MASK register. A push or pop instruction saves
or restores both bytes (PSW + INT_MASK).
PTS Peripheral transaction server. The microcoded
hardware interrupt processor.
PTSCB See PTS control block.
PTS control block A block of data required for each PTS interrupt. The
microcode executes the proper PTS routine based on
the contents of the PTS control block.
PTS cycle The microcoded response to a single PTS interrupt
request.
PTS interrupt Any maskable interrupt that is assigned to the PTS for
interrupt processing.
PTS mode A microcoded response that enables the PTS to
complete a specific task quickly. These tasks include
transferring a single byte or word, transferring a block
of bytes or words, and generating PWM outputs.
PTS routine The entire microcoded response to multiple PTS
interrupt requests. The PTS routine is controlled by
the contents of the PTS control block.
PTS transfer The movement of a single byte or word from the
source memory location to the destination memory
location.
PTS vector A location in special-purpose memory that holds the
starting address of a PTS control block.
QUAD-WORD An unsigned, 64-bit variable with values from 0
through 2
64
–1. The QUAD-WORD variable is
supported only as the operand for the EBMOVI
instruction.
RALU Register arithmetic-logic unit. A part of the CPU that
consists of the ALU, the PSW, the master PC, the
microcode engine, a loop counter, and six registers.