Filter
Top Products
8XC196NP, 80C196NU USER’S MANUAL
4-6
EST Extended store word. Stores the value of the source (leftmost) word operand
into the destination (rightmost) operand. This instruction allows you to move
data from the lower register file to anywhere in the address space. It operates in
extended indirect and extended indexed modes.
ESTB Extended store byte. Stores the value of the source (leftmost) byte operand into
the destination (rightmost) operand. This instruction allows you to move data
from the lower register file to anywhere in the address space. It operates in
extended indirect and extended indexed modes.
4.2 ADDRESSING MODES
The instruction set uses four basic addressing modes:
• direct
• immediate
• indirect (with or without autoincrement)
• indexed (short-, long-, or zero-indexed)
The stack pointer can be used with indirect addressing to access the top of the stack, and it can
also be used with short-indexed addressing to access data within the stack. The zero register can
be used with long-indexed addressing to access any memory location.
Extended variations of the indirect and indexed modes support the extended load and store in-
structions. An extended load instruction moves a word (ELD) or a byte (ELDB) from any location
in the address space into the lower register file. An extended store instruction moves a word
(EST) or a byte (ESTB) from the lower register file into any location in the address space. An
instruction can contain only one immediate, indirect, or indexed reference; any remaining oper-
ands must be direct references.
This section describes the addressing modes as they are handled by the hardware. An understand-
ing of these details will help programmers to take full advantage of the architecture. The assembly
language hides some of the details of how these addressing modes work. “Assembly Language
Addressing Mode Selections” on page 4-11 describes how the assembly language handles direct
and indexed addressing modes.
The examples in this section assume that temporary registers are defined as shown in this segment
of assembly code and described in Table 4-3.
Oseg at 1ch
AX DSW 1
BX DSW 1
CX DSW 1
DX DSW 1
EX DSL 1