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8XC196NP, 80C196NU USER’S MANUAL
A-56
Data
Mnemonic
Direct Immediate Extended-indirect
Extended-
indexed
Length Opcode Length Opcode Length Opcode Length Opcode
EBMOVI ———— 3E4——
ELD ———— 3E86E9
ELDB ———— 3EA6EB
EST ———— 31C61D
ESTB ———— 31E61F
Mnemonic
Direct Immediate
Indirect
(Note 1)
Indexed
(Notes 1, 2)
Length Opcode Length Opcode Length Opcode
Length
S/L
Opcode
BMOV ———— 3C1——
BMOVI ———— 3CD——
LD 3A04A13A24/5A3
LDB 3B03B13B24/5B3
LDBSE 3 BC 3 BD 3 BE 4/5 BF
LDBZE 3 AC 3 AD 3 AE 4/5 AF
ST 3 C0 — — 3 C2 4/5 C3
STB 3 C4 — — 3 C6 4/5 C7
XCH 304————4/50B
XCHB 314————4/51B
Table A-8. Instruction Lengths and Hexadecimal Opcodes (Continued)
NOTES:
1. Indirect normal and indirect autoincrement share the same opcodes, as do short- and long-indexed
modes. Because word registers always have even addresses, the address can be expressed in the
upper seven bits; the least-significant bit determines the addressing mode. Indirect normal and short-
indexed modes make the second byte of the instruction even (LSB = 0). Indirect autoincrement and
long-indexed modes make the second byte odd (LSB = 1).
2. For indexed instructions, the first column lists instruction lengths as
S
/
L
, where
S
is the short-indexed
instruction length and
L
is the long-indexed instruction length.
3. For the SCALL and SJMP instructions, the three least-significant bits of the opcode are concatenated
with the eight bits to form an 11-bit, 2’s complement offset.