Filter
Top Products
A-55
INSTRUCTION SET REFERENCE
Stack
Mnemonic
Direct Immediate
Indirect
(Note 1)
Indexed
(Notes 1, 2)
Length Opcode Length Opcode Length Opcode
Length
S/L
Opcode
POP 2 CC — — 2 CE 3/4 CF
POPA 1F5——————
POPF 1F3——— ———
PUSH 2 C8 3 C9 2 CA 3/4 CB
PUSHA 1F4——————
PUSHF 1F2——————
Table A-8. Instruction Lengths and Hexadecimal Opcodes (Continued)
NOTES:
1. Indirect normal and indirect autoincrement share the same opcodes, as do short- and long-indexed
modes. Because word registers always have even addresses, the address can be expressed in the
upper seven bits; the least-significant bit determines the addressing mode. Indirect normal and short-
indexed modes make the second byte of the instruction even (LSB = 0). Indirect autoincrement and
long-indexed modes make the second byte odd (LSB = 1).
2. For indexed instructions, the first column lists instruction lengths as
S
/
L
, where
S
is the short-indexed
instruction length and
L
is the long-indexed instruction length.
3. For the SCALL and SJMP instructions, the three least-significant bits of the opcode are concatenated
with the eight bits to form an 11-bit, 2’s complement offset.