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8XC196NP, 80C196NU USER’S MANUAL
xii
FIGURES
Figure Page
8-5 Serial Port Frames in Mode 2 and 3.............................................................................8-7
8-6 Serial Port Control (SP_CON) Register........................................................................8-9
8-7 Serial Port Baud Rate (SP_BAUD) Register..............................................................8-11
8-8 Serial Port Status (SP_STATUS) Register.................................................................8-14
9-1 PWM Block Diagram (8XC196NP Only).......................................................................9-1
9-2 PWM Block Diagram (80C196NU Only).......................................................................9-2
9-3 PWM Output Waveforms..............................................................................................9-5
9-4 Control (CON_REG0) Register ....................................................................................9-7
9-5 PWM Control (PWM
x
_CONTROL) Register ................................................................9-8
9-6 D/A Buffer Block Diagram...........................................................................................9-10
9-7 PWM to Analog Conversion Circuitry .........................................................................9-10
10-1 EPA Block Diagram....................................................................................................10-2
10-2 EPA Timer/Counters ..................................................................................................10-5
10-3 Quadrature Mode Interface ........................................................................................10-7
10-4 Quadrature Mode Timing and Count..........................................................................10-8
10-5 A Single EPA Capture/Compare Channel..................................................................10-9
10-6 EPA Simplified Input-capture Structure....................................................................10-10
10-7 Valid EPA Input Events ............................................................................................10-10
10-8 Timer 1 Control (T1CONTROL) Register.................................................................10-16
10-9 Timer 2 Control (T2CONTROL) Register.................................................................10-17
10-10 EPA Control (EPA
x
_CON) Registers.......................................................................10-19
10-11 EPA Interrupt Mask (EPA_MASK) Register.............................................................10-22
10-12 EPA Interrupt Pending (EPA_PEND) Register.........................................................10-23
11-1 Minimum Hardware Connections ...............................................................................11-3
11-2 Power and Return Connections .................................................................................11-4
11-3 On-chip Oscillator Circuit............................................................................................11-5
11-4 External Crystal Connections .....................................................................................11-6
11-5 External Clock Connections .......................................................................................11-7
11-6 External Clock Drive Waveforms................................................................................11-7
11-7 Reset Timing Sequence.............................................................................................11-8
11-8 Internal Reset Circuitry...............................................................................................11-9
11-9 Minimum Reset Circuit .............................................................................................11-10
11-10 Example System Reset Circuit.................................................................................11-10
12-1 Clock Control During Power-saving Modes (8XC196NP) ..........................................12-4
12-2 Clock Control During Power-saving Modes (80C196NU)...........................................12-5
12-3 Power-up and Powerdown Sequence When Using an External Interrupt..................12-9
12-4 External RC Circuit.....................................................................................................12-9
12-5 Typical Voltage on the RPD Pin While Exiting Powerdown.....................................12-11
13-1 Calculation of a Chip-select Output............................................................................13-6
13-2 Address Compare (ADDRCOM
x
) Register ................................................................13-7
13-3 Address Mask (ADDRMSK
x
) Register .......................................................................13-8
13-4 Bus Control (BUSCON
x
) Register............................................................................13-10
13-5 Example System for Setting Up Chip-select Outputs...............................................13-13
13-6 Chip Configuration 0 (CCR0) Register .....................................................................13-15