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8XC196NP, 80C196NU USER’S MANUAL
The 8XC196NP allows you to change the value of EP_REG to control which memory page a non-
extended instruction accesses. However, software tools require that EP_REG be equal to 00H.
The 80C196NU forces all nonextended data accesses to page 00H. You cannot use EP_REG to
change pages.
You can read EP_PIN at any time to determine the value of a pin. When EP_PIN is read, the con-
tents of the sample latch are output onto the internal bus.
Figure 7-3 shows a circuit schematic for a single bit of the EPORT. Q1 and Q2 are the strong com-
plementary drivers for the pin. Q1
can source at least –3 mA at V
CC
– 0.7 volts. Q2 can sink at
least 3 mA at V
SS
+ 0.45 volts. (Consult the datasheet for specifications.) Resistor R1 provides
ESD protection for the pin.
7.3.1.1 Reset
During reset, the falling edge of RESET# generates a short pulse that turns on the medium pull-
up transistor Q3, which remains on for about 300 ns, causing the pin to change rapidly to its reset
state. The active-low level of RESET# turns on transistor Q4, which weakly holds the pin high.
(Q4 can source approximately –10 µΑ; consult the datasheet for exact specifications.) When
RESET# is inactive, both Q3 and Q4 are off; Q1 and Q2 determine output drive.
7.3.1.2 Output Enable
If RESET#, HOLD#, idle, or powerdown is asserted, the gates that control Q1 and Q2 are dis-
abled and Q1 and Q2 remain off. Otherwise, the gates are enabled and complementary or open-
drain operation is possible.
7.3.1.3 Complementary Output Mode
For complementary output mode, the gates that control Q1 and Q2 must be enabled. The Q2 gate
is always enabled (except when RESET#, HOLD#, idle, or powerdown is asserted). Either clear-
ing EP_DIR (selecting complementary mode) or setting EP_MODE (selecting address mode) en-
ables the logic gate preceding Q1. The value of DATA determines which transistor is turned on.
If DATA is equal to one, Q1 is turned on and the pin is pulled high. If DATA is equal to zero, Q2
is turned on and the pin is pulled low.
7.3.1.4 Open-drain Output Mode
For open-drain output mode, the gate that controls Q1 must be disabled. Setting EP_DIR (select-
ing open-drain mode) and clearing EP_MODE (selecting I/O mode) disables the logic gate pre-
ceding Q1. The value of DATA determines whether Q2 is turned on. If DATA is equal to one, both
Q1 and Q2 remain off and the pin is left in high-impedance state (floating). If DATA is equal to
zero, Q2 is turned on and the pin is pulled low.