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I/O PORTS
7.2.5 Design Considerations for External Interrupt Inputs
To configure a port pin that serves as an external interrupt input, you must set the corresponding
bits in the configuration registers (Px_DIR, Px_MODE, and Px_REG). However, setting the
Px_MODE bit causes the device to set the corresponding interrupt pending bit, indicating an in-
terrupt request. To configure P2.2/EXTINT0, P2.4/EXTINT1, P3.6/EXTINT2, and
P3.7/EXTINT3, we recommend the following sequence to prevent the false interrupt request:
1. Disable interrupts by executing the DI instruction.
2. Set the Px_DIR bit.
3. Set the Px_MODE bit.
4. Set the Px_REG bit.
5. Clear the INT_PEND and INT_PEND1 bits.
6. Enable interrupts (optional) by executing the EI instruction.
7.3 EPORT
The EPORT is a four-bit, bidirectional, memory-mapped I/O port in the 8XC196NP, but a stan-
dard I/O port in the 80C196NU. For the 8XC196NP, it must be accessed using indirect or indexed
addressing, and it cannot be windowed. For the 80C196NU, it can be windowed. This port pro-
vides the address signals necessary to support extended addressing. If one or more extended ad-
dress pins are unnecessary in an application, the unused port pins can be used for I/O. Figure 7-2
shows a block diagram of the EPORT.
Table 7-9 lists the EPORT pins with their extended-address signals. Table 7-10 lists the registers
that affect the function and indicate the status of EPORT pins.
Table 7-9. EPORT Pins
Port Pin
Extended-address
Signal
Signal Type
EPORT.0 A16 I/O
EPORT.1 A17 I/O
EPORT.2 A18 I/O
EPORT.3 A19 I/O