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8XC196NP, 80C196NU USER’S MANUAL
6-6
6.3.1.3 NMI
The external NMI pin generates a nonmaskable interrupt for implementation of critical interrupt
routines. NMI has the highest priority of all the prioritized interrupts. It is passed directly from
the transition detector to the priority encoder, and it vectors indirectly through location FF203EH.
The NMI pin is sampled during phase 2 (CLKOUT high) and is latched internally. Because inter-
rupts are edge-triggered, only one interrupt is generated, even if the pin is held high. If your sys-
tem does not use the NMI interrupt, connect the NMI pin to V
SS
to prevent spurious interrupts.
6.3.2 External Interrupt Pins
The external interrupt pins are multiplexed with port pins as follows: EXTINT0/P2.2,
EXTINT1/P2.4, EXTINT2/P3.6, and EXTINT3/P3.7. Writing to a bit in the Px_MODE register
also sets the corresponding external interrupt bit in the interrupt pending register. To prevent false
interrupts, first configure the port pins and then clear the interrupt pending registers before glo-
bally enabling interrupts. See “Design Considerations for External Interrupt Inputs” on page
7-11.
The interrupt detection logic can generate an interrupt if a momentary negative glitch occurs
while the input pin is held high. For this reason, interrupt inputs should normally be held low
when they are inactive.
6.3.3 Multiplexed Interrupt Sources
The overrun errors for the four capture/compare modules are multiplexed into two interrupt pairs:
OVR0_1 (channels 0 and 1) and OVR2_3 (channels 2 and 3). Generally, PTS interrupt service is
not useful for multiplexed interrupts because the PTS cannot readily determine the interrupt
source. Your interrupt service routine should read the EPA_PEND register to determine the
source of the interrupt and to ensure that no additional interrupts are pending before executing the
return instruction. Chapter 10, “Event Processor Array (EPA),” discusses the EPA interrupts in
detail.
6.3.4 End-of-PTS Interrupts
When the PTSCOUNT register decrements to zero at the end of a single transfer or block transfer
routine, hardware clears the corresponding bit in the PTSSEL register, which disables PTS service
for that interrupt. It also sets the corresponding PTSSRV bit, requesting an end-of-PTS interrupt.
An end-of-PTS interrupt has the same priority as a corresponding standard interrupt. The interrupt
controller processes it with an interrupt service routine that is stored in the memory location
pointed to by the standard interrupt vector. For example, the PTS services the SIO transmit inter-