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7-5
I/O PORTS
Figure 7-1. Bidirectional Port Structure
Vcc
Q2
Q1
Px_REG
Px_DIR
Sample
Latch
PH1 Clock
Internal Bus
SFDATA
SFDIR
Px_MODE
Px_PIN
DQ
0
1
0
1
Vcc
Vcc
Q
R
S
Any Write to Px_MODE
Weak
Pullup
Medium
Pullup
RESET#
RESET#
Q3
Q4
Vss
Read Port
LE
300ns Delay
I/O Pin
A0238-04
150Ω to 200Ω
R1