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INTERFACING WITH EXTERNAL MEMORY
Figure 13-14. READY Timing Diagram — Demultiplexed Mode (8XC196NP)
T0007-02
T
CLYX
(max)
T
AVDV
+ 2t
T
WLWH
+ 2t
T
AVYV
T
LHLH
+ 2t
T
RLRH
+ 2t
T
RLDV
+ 2t
T
QVWH
+ 2t
Data
Data Valid
CLKOUT
READY
ALE
RD#
AD15:0
WR#
AD15:0
BHE#, INST
A19:0
CS
x
#
T
CLYX
(min)
(read)
(write)