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Model GFC7000E Instruction Manual THEORY OF OPERATION
04584 Rev A1 167
The four sample and hold circuits are:
ACTIVE WHEN: DESIGNATION
IR BEAM PASSING THROUGH SEGMENT SENSOR PULSE IS:
Measure Gate MEASUREMENT cell of GFC Wheel HIGH
Measure Dark Gate MEASUREMENT Cell of GFC Wheel LOW
Reference Gate REFERENCE cell of GFC Wheel HIGH
Reference Dark Gate REFERENCE cell of GFC Wheel LOW
Timing for activating the Sample and Hold circuits is provided by a phase lock loop circuit (PLL).
Using the segment sensor output as a reference signal the PLL generates clock signal at ten times
that frequency. This faster clock signal is used by the PLD to make the sample and hold circuits
capture the signal during the center portions of the detected waveform, ignore the rising and
falling edges of the detector signal.
Sample & Hold
Active
Detector
Out
p
ut
Sample & Hold
Inactive
Figure 10-13: Sample & Hold Timing
10.3.4.3. Phase Lock Warning
In order to detect critical fault conditions such as a failure of either the segment sensor or the GFC
wheel motor, the synch/demod board also performs a simple check of the above signal
synchronization to make sure everything is operation. The PLD divides the X10 clock signal by ten
and sends this signal back to the PLL circuit which compares it to the original segment sensor
reference signal.
If these two signals match, the PLL sends a status level to the PLD that the phase lock is OK. If
for some reason the two signals do not match, the PLL alerts the PLD that phase lock has been
lost and the PLD issues a phase lock warning to the CPU. Should this occur, A SYNC warning will
appear on the analyzer’s front panel display (see Section 11.1.1 for more information).
10.3.4.4. Sync/Demod Status LED’s
The following two status LED’s located on the synch/demod board provide additional diagnostic
tools for checking the GFC wheel rotation.