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A-57
INSTRUCTION SET REFERENCE
Shift
Mnemonic Direct
NORML 8 + 1 per shift (9 for 0 shift)
SHL 6 + 1 per shift (7 for 0 shift)
SHLB 6 + 1 per shift (7 for 0 shift)
SHLL 7 + 1 per shift (8 for 0 shift)
SHR 6 + 1 per shift (7 for 0 shift)
SHRA 6 + 1 per shift (7 for 0 shift)
SHRAB 6 + 1 per shift (7 for 0 shift)
SHRAL 7 + 1 per shift (8 for 0 shift)
SHRB 6 + 1 per shift (7 for 0 shift)
SHRL 7 + 1 per shift (8 for 0 shift)
Special
Mnemonic Direct Immed.
Indirect Indexed
Normal Autoinc. Short Long
CLRC 2—————
CLRVT 2—————
DI 2—————
EI 2—————
IDLPD
Valid key
Invalid key
—
—
12
28
—
—
—
—
—
—
—
—
NOP 2—————
RST 4—————
SETC 2—————
SKIP 3—————
PTS
Mnemonic Direct Immed.
Indirect Indexed
Normal Autoinc. Short Long
DPTS 2 — — — — —
EPTS 2—————
Table A-9. Instruction Execution Times (in State Times) (Continued)
NOTE: The column entitled “Reg.” lists the instruction execution times for accesses to the register file or
peripheral SFRs. The column entitled “Mem.” lists the instruction execution times for accesses to
all memory-mapped registers, I/O, or memory. See Table 4-1 on page 4-2 for address information.