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© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
User manual Rev. 02 — 23 May 2005 99 of 133
Philips Semiconductors
UM10109
P89LPC932A1 User manual
Figure 49 shows the watchdog timer in watchdog mode. It consists of a programmable
13-bit prescaler, and an 8-bit down counter. The down counter is clocked (decremented)
by a tap taken from the prescaler. The clock source for the prescaler is either PCLK or the
watchdog oscillator selected by the WDCLK bit in the WDCON register. (Note that
switching of the clock sources will not take effect immediately - see Section 15.3
).
The watchdog asserts the watchdog reset when the watchdog count underflows and the
watchdog reset is enabled. When the watchdog reset is enabled, writing to WDL or
WDCON must be followed by a feed sequence for the new values to take effect.
If a watchdog reset occurs, the internal reset is active for at least one watchdog clock
cycle (PCLK or the watchdog oscillator clock). If CCLK is still running, code execution will
begin immediately after the reset cycle. If the processor was in Power-down mode, the
watchdog reset will start the oscillator and code execution will resume after the oscillator
is stable.
15.2 Feed sequence
The watchdog timer control register and the 8-bit down counter (See Figure 48) are not
directly loaded by the user. The user writes to the WDCON and the WDL SFRs. At the end
of a feed sequence, the values in the WDCON and WDL SFRs are loaded to the control
register and the 8-bit down counter. Before the feed sequence, any new values written to
Table 86: Watchdog timer configuration
WDTE WDSE FUNCTION
0 x The watchdog reset is disabled. The timer can be used as an internal timer and
can be used to generate an interrupt. WDSE has no effect.
1 0 The watchdog reset is enabled. The user can set WDCLK to choose the clock
source.
1 1 The watchdog reset is enabled, along with additional safety features:
1. WDCLK is forced to 1 (using watchdog oscillator)
2. WDCON and WDL register can only be written once
3. WDRUN is forced to 1
Fig 47. Watchdog Prescaler.
÷2 ÷2 ÷2 ÷2 ÷2 ÷2 ÷2
PRE2
PRE1
PRE0
watchdog
oscillator
PCLK
÷32
÷64÷32 ÷128 ÷256 ÷512 ÷1024 ÷2048 ÷4096
to watchdog
down counter
(after one prescaler
count delay)
DECODE
002aaa938
000
001
010
011
100
101
110
111
WDCLK AFTER
A WATCHDOG
FEED SEQUENCE