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© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
User manual Rev. 02 — 23 May 2005 14 of 133
Philips Semiconductors
UM10109
P89LPC932A1 User manual
Table 2: P89LPC932A1 Special function registers
* indicates SFRs that are bit addressable.
Name Description SFR
addr.
Bit functions and addresses Reset value
MSB LSB Hex Binary
Bit address E7 E6 E5 E4 E3 E2 E1 E0
ACC* Accumulator E0H 00 0000 0000
AUXR1 Auxiliary function register A2H CLKLP EBRR ENT1 ENT0 SRST 0 - DPS 00 0000 00x0
Bit address F7 F6 F5 F4 F3 F2 F1 F0
B* B register F0H 00 0000 0000
BRGR0
[2]
Baud rate generator rate
low
BEH 00 0000 0000
BRGR1
[2]
Baud rate generator rate
high
BFH 00 0000 0000
BRGCON Baud rate generator
control
BDH------SBRGSBRGEN00
[2]
xxxx xx00
CCCRA Capture compare A control
register
EAH ICECA2 ICECA1 ICECA0 ICESA ICNFA FCOA OCMA1 OCMA0 00 0000 0000
CCCRB Capture compare B control
register
EBH ICECB2 ICECB1 ICECB0 ICESB ICNFB FCOB OCMB1 OCMB0 00 0000 0000
CCCRC Capture compare C control
register
ECH-----FCOCOCMC1OCMC000xxxxx000
CCCRD Capture compare D control
register
EDH-----FCODOCMD1OCMD000xxxxx000
CMP1 Comparator 1 control
register
ACH - - CE1 CP1 CN1 OE1 CO1 CMF1 00
[1]
xx00 0000
CMP2 Comparator 2 control
register
ADH - - CE2 CP2 CN2 OE2 CO2 CMF2 00
[1]
xx00 0000
DEECON Data EEPROM control
register
F1H EEIF HVERR ECTL1 ECTL0 - - - EADR8 0E 0000 1110
DEEDAT Data EEPROM data
register
F2H 00 0000 0000
DEEADR Data EEPROM address
register
F3H 00 0000 0000
DIVM CPU clock divide-by-M
control
95H 00 0000 0000
DPTR Data pointer (2 bytes)