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© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
User manual Rev. 02 — 23 May 2005 19 of 133
Philips Semiconductors
UM10109
P89LPC932A1 User manual
[1] All ports are in input only (high-impedance) state after power-up.
[2] BRGR1 and BRGR0 must only be written if BRGEN in BRGCON SFR is logic 0. If any are written while BRGEN = 1, the result is unpredictable.
[3] The RSTSRC register reflects the cause of the P89LPC932A1 reset. Upon a power-up reset, all reset source flags are cleared except POF and BOF; the power-on reset value is
xx110000.
[4] After reset, the value is 111001x1, i.e., PRE2-PRE0 are all logic 1, WDRUN = 1 and WDCLK = 1. WDTOF bit is logic 1 after watchdog reset and is logic 0 after power-on reset.
Other resets will not affect WDTOF.
[5] On power-on reset, the TRIM SFR is initialized with a factory preprogrammed value. Other resets will not cause initialization of the TRIM register.
[6] The only reset source that affects these SFRs is power-on reset.
TPCR2L Prescaler control register
low
CAH TPCR2L.
7
TPCR2L.
6
TPCR2L.
5
TPCR2L.
4
TPCR2L.
3
TPCR2L.
2
TPCR2L.
1
TPCR2L.
0
00 0000 0000
TRIM Internal oscillator trim
register
96H RCCLK ENCLK TRIM.5 TRIM.4 TRIM.3 TRIM.2 TRIM.1 TRIM.0
[5]
[6]
WDCON Watchdog control register A7H PRE2 PRE1 PRE0 - - WDRUN WDTOF WDCLK
[4]
[6]
WDL Watchdog load C1H FF 1111 1111
WFEED1 Watchdog feed 1 C2H
WFEED2 Watchdog feed 2 C3H
Table 2: P89LPC932A1 Special function registers
…continued
* indicates SFRs that are bit addressable.
Name Description SFR
addr.
Bit functions and addresses Reset value
MSB LSB Hex Binary