Filter
Top Products
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
User manual Rev. 02 — 23 May 2005 66 of 133
Philips Semiconductors
UM10109
P89LPC932A1 User manual
– If DBISEL is logic 1 and INTLO is logic 0, a Tx interrupt will occur at the beginning
of the STOP bit of the data currently in the shifter (which is also the last data).
– If DBISEL is logic 1 and INTLO is logic 1, a Tx interrupt will occur at the end of the
STOP bit of the data currently in the shifter (which is also the last data).
– Note that if DBISEL is logic 1 and the CPU is writing to SBUF when the STOP bit of
the last data is shifted out, there can be an uncertainty of whether a Tx interrupt is
generated already with the UART not knowing whether there is any more data
following.
6. If there is more data, the CPU writes to SBUF again. Then:
– If INTLO is logic 0, the new data will be loaded and a Tx interrupt will occur at the
beginning of the STOP bit of the data currently in the shifter.
– If INTLO is logic 1, the new data will be loaded and a Tx interrupt will occur at the
end of the STOP bit of the data currently in the shifter.
– Go to 3.
10.18 The 9th bit (bit 8) in double buffering (Modes 1, 2, and 3)
If double buffering is disabled (DBMOD, i.e. SSTAT.7 = 0), TB8 can be written before or
after SBUF is written, provided TB8 is updated before that TB8 is shifted out. TB8 must
not be changed again until after TB8 shifting has been completed, as indicated by the Tx
interrupt.
Fig 29. Transmission with and without double buffering.
TxD
write to
SBUF
Tx interrupt
single buffering (DBMOD/SSTAT.7 = 0), early interrupt (INTLO/SSTAT.6 = 0) is shown
TxD
write to
SBUF
Tx interrupt
double buffering (DBMOD/SSTAT.7 = 1), early interrupt (INTLO/SSTAT.6 = 0) is shown,
no ending Tx interrupt (DBISEL/SSTAT.4 = 0)
TxD
write to
SBUF
Tx interrupt
double buffering (DBMOD/SSTAT.7 = 1), early interrupt (INTLO/SSTAT.6 = 0) is shown,
with ending Tx interrupt (DBISEL/SSTAT.4 = 1)
002aaa92
8