Filter
Top Products
© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
User manual Rev. 02 — 23 May 2005 25 of 133
Philips Semiconductors
UM10109
P89LPC932A1 User manual
3.1 Interrupt priority structure
There are four SFRs associated with the four interrupt levels: IP0, IP0H, IP1, IP1H. Every
interrupt has two bits in IPx and IPxH (x = 0, 1) and can therefore be assigned to one of
four levels, as shown in Table 7
.
The P89LPC932A1 has two external interrupt inputs in addition to the Keypad Interrupt
function. The two interrupt inputs are identical to those present on the standard 80C51
microcontrollers.
These external interrupts can be programmed to be level-triggered or edge-triggered by
clearing or setting bit IT1 or IT0 in Register TCON. If ITn = 0, external interrupt n is
triggered by a low level detected at the INTn
pin. If ITn = 1, external interrupt n is edge
triggered. In this mode if consecutive samples of the INTn
pin show a high level in one
cycle and a low level in the next cycle, interrupt request flag IEn in TCON is set, causing
an interrupt request.
Since the external interrupt pins are sampled once each machine cycle, an input high or
low level should be held for at least one machine cycle to ensure proper sampling. If the
external interrupt is edge-triggered, the external source has to hold the request pin high
for at least one machine cycle, and then hold it low for at least one machine cycle. This is
to ensure that the transition is detected and that interrupt request flag IEn is set. IEn is
automatically cleared by the CPU when the service routine is called.
If the external interrupt is level-triggered, the external source must hold the request active
until the requested interrupt is generated. If the external interrupt is still asserted when the
interrupt service routine is completed, another interrupt will be generated. It is not
necessary to clear the interrupt flag IEn when the interrupt is level sensitive, it simply
tracks the input pin level.
If an external interrupt has been programmed as level-triggered and is enabled when the
P89LPC932A1 is put into Power-down mode or Idle mode, the interrupt occurrence will
cause the processor to wake-up and resume operation. Refer to Section 5.3 “
Power
reduction modes” for details.
3.2 External Interrupt pin glitch suppression
Most of the P89LPC932A1 pins have glitch suppression circuits to reject short glitches
(please refer to the P89LPC932A1 data sheet, Dynamic characteristics for glitch filter
specifications). However, pins SDA/INT0
/P1.3 and SCL/T0/P1.2 do not have the glitch
suppression circuits. Therefore, INT1
has glitch suppression while INT0 does not.
Table 6: Interrupt priority level
Priority bits
IPxH IPx Interrupt priority level
0 0 Level 0 (lowest priority)
01Level 1
10Level 2
11Level 3