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© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
User manual Rev. 02 — 23 May 2005 24 of 133
Philips Semiconductors
UM10109
P89LPC932A1 User manual
2.8 CPU Clock (CCLK) modification: DIVM register
The OSCCLK frequency can be divided down, by an integer, up to 510 times by
configuring a dividing register, DIVM, to provide CCLK. This produces the CCLK
frequency using the following formula:
CCLK frequency = f
osc
/ (2N)
Where: f
osc
is the frequency of OSCCLK, N is the value of DIVM.
Since N ranges from 0 to 255, the CCLK frequency can be in the range of f
osc
to f
osc
/510.
(for N = 0, CCLK = f
osc
).
This feature makes it possible to temporarily run the CPU at a lower rate, reducing power
consumption. By dividing the clock, the CPU can retain the ability to respond to events
other than those that can cause interrupts (i.e. events that allow exiting the Idle mode) by
executing its normal program at a lower rate. This can often result in lower power
consumption than in Idle mode. This can allow bypassing the oscillator start-up time in
cases where Power-down mode would otherwise be used. The value of DIVM may be
changed by the program at any time without interrupting code execution.
2.9 Low power select
The P89LPC932A1 is designed to run at 12 MHz (CCLK) maximum. However, if CCLK is
8 MHz or slower, the CLKLP SFR bit (AUXR1.7) can be set to a logic 1 to lower the power
consumption further. On any reset, CLKLP is logic 0 allowing highest performance. This
bit can then be set in software if CCLK is running at 8 MHz or slower.
3. Interrupts
The P89LPC932A1 uses a four priority level interrupt structure. This allows great flexibility
in controlling the handling of the P89LPC932A1’s 15 interrupt sources.
Each interrupt source can be individually enabled or disabled by setting or clearing a bit in
the interrupt enable registers IEN0 or IEN1. The IEN0 register also contains a global
enable bit, EA, which enables all interrupts.
Each interrupt source can be individually programmed to one of four priority levels by
setting or clearing bits in the interrupt priority registers IP0, IP0H, IP1, and IP1H. An
interrupt service routine in progress can be interrupted by a higher priority interrupt, but
not by another interrupt of the same or lower priority. The highest priority interrupt service
cannot be interrupted by any other interrupt source. If two requests of different priority
levels are received simultaneously, the request of higher priority level is serviced.
If requests of the same priority level are pending at the start of an instruction cycle, an
internal polling sequence determines which request is serviced. This is called the
arbitration ranking. Note that the arbitration ranking is only used for pending requests of
the same priority level. Ta bl e 7
summarizes the interrupt sources, flag bits, vector
addresses, enable bits, priority bits, arbitration ranking, and whether each interrupt may
wake-up the CPU from a Power-down mode.