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© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
User manual Rev. 02 — 23 May 2005 41 of 133
Philips Semiconductors
UM10109
P89LPC932A1 User manual
Table 23: Timer/Counter Control register (TCON) - address 88h) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol TF1 TR1 TF0 TR0 IE1 IT1 IE0 IT0
Reset00000000
Table 24: Timer/Counter Control register (TCON - address 88h) bit description
Bit Symbol Description
0 IT0 Interrupt 0 Type control bit. Set/cleared by software to specify falling edge/low level triggered external
interrupts.
1 IE0 Interrupt 0 Edge flag. Set by hardware when external interrupt 0 edge is detected. Cleared by hardware
when the interrupt is processed, or by software.
2 IT1 Interrupt 1 Type control bit. Set/cleared by software to specify falling edge/low level triggered external
interrupts.
3 IE1 Interrupt 1 Edge flag. Set by hardware when external interrupt 1 edge is detected. Cleared by hardware
when the interrupt is processed, or by software.
4 TR0 Timer 0 Run control bit. Set/cleared by software to turn Timer/Counter 0 on/off.
5 TF0 Timer 0 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the processor
vectors to the interrupt routine, or by software. (except in mode 6, where it is cleared in hardware)
6 TR1 Timer 1 Run control bit. Set/cleared by software to turn Timer/Counter 1 on/off
7 TF1 Timer 1 overflow flag. Set by hardware on Timer/Counter overflow. Cleared by hardware when the interrupt
is processed, or by software (except in mode 6, see above, when it is cleared in hardware).
Fig 14. Timer/counter 0 or 1 in Mode 0 (13-bit counter).
002aaa919
PCLK
Tn pin
TRn
gate
INTn pin
C/T = 0
C/T = 1
TLn
(5-bits)
THn
(8-bits)
TFn
control
ENTn
Tn pin
toggle
overflow
interrupt
Fig 15. Timer/counter 0 or 1 in mode 1 (16-bit counter).
002aaa920
PCLK
Tn pin
TRn
gate
INTn pin
C/T = 0
C/T = 1
TLn
(8-bits)
THn
(8-bits)
TFn
control
ENTn
Tn pin
toggle
overflow
interrupt