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© Koninklijke Philips Electronics N.V. 2005. All rights reserved.
User manual Rev. 02 — 23 May 2005 60 of 133
Philips Semiconductors
UM10109
P89LPC932A1 User manual
10.7 Updating the BRGR1 and BRGR0 SFRs
The baud rate SFRs, BRGR1 and BRGR0 must only be loaded when the Baud Rate
Generator is disabled (the BRGEN bit in the BRGCON register is logic 0). This avoids the
loading of an interim value to the baud rate generator. (CAUTION: If either BRGR0 or
BRGR1 is written when BRGEN = 1, the result is unpredictable.)
10.8 Framing error
A Framing error occurs when the stop bit is sensed as a logic 0. A Framing error is
reported in the status register (SSTAT). In addition, if SMOD0 (PCON.6) is 1, framing
errors can be made available in SCON.7. If SMOD0 is 0, SCON.7 is SM0. It is
recommended that SM0 and SM1 (SCON[7:6]) are programmed when SMOD0 is logic 0.
Table 47: UART baud rate generation
SCON.7
(SM0)
SCON.6
(SM1)
PCON.7
(SMOD1)
BRGCON.1
(SBRGS)
Receive/transmit baud rate for UART
00XX
CCLK
⁄
16
0100
CCLK
⁄
(256−TH1)64
10
CCLK
⁄
(256−TH1)32
X1
CCLK
⁄
((BRGR1, BRGR0)+16)
100X
CCLK
⁄
32
1X
CCLK
⁄
16
1100
CCLK
⁄
(256−TH1)64
10
CCLK
⁄
(256−TH1)32
X1
CCLK
⁄
((BRGR1, BRGR0)+16)
Table 48: Baud Rate Generator Control register (BRGCON - address BDh) bit allocation
Bit 7 6 5 4 3 2 1 0
Symbol-------SBRGSBRGEN
Resetxxxxxx0 0
Table 49: Baud Rate Generator Control register (BRGCON - address BDh) bit description
Bit Symbol Description
0 BRGEN Baud Rate Generator Enable. Enables the baud rate generator. BRGR1 and
BRGR0 can only be written when BRGEN = 0.
1 SBRGS Select Baud Rate Generator as the source for baud rates to UART in modes 1 and
3 (see Tabl e 47
for details)
2:7 - reserved
Fig 25. Baud rate generation for UART (Modes 1, 3).
baud rate modes 1 and 3
SBRGS = 1
SBRGS = 0
SMOD1 = 0
SMOD1 = 1
timer 1 overflow
(PCLK-based)
baud rate generator
(CCLK-based)
002aaa897
÷2