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8XC196MC, MD, MH USER’S MANUAL
5-10
Each PTS cycle within a PTS routine cannot be interrupted. A PTS cycle is the entire PTS re-
sponse to a single interrupt request. In block transfer mode, a PTS cycle consists of the transfer
of an entire block of bytes or words. This means a worst-case latency of 500 states if you assume
a block transfer of 32 words from one external memory location to another. See Table 5-4 on page
5-12 for PTS cycle execution times.
5.4.2 Calculating Latency
The maximum latency occurs when the interrupt request occurs too late for acknowledgment fol-
lowing the current instruction. The following worst-case calculation assumes that the current in-
struction is not a protected instruction. To calculate latency, add the following terms:
• Time for the current instruction to finish execution (4 state times).
— If this is a protected instruction, the instruction that follows it must also execute before
the interrupt can be acknowledged. Add the execution time of the instruction that
follows a protected instruction.
• Time for the next instruction to execute. (The longest instruction, NORML, takes 39 state
times. However, the BMOV instruction could actually take longer if it is transferring a large
block of data. If your code contains routines that transfer large blocks of data, you may get a
more accurate worst-case value if you use the BMOV instruction in your calculation instead
of NORML. See Appendix A for instruction execution times.)
• For standard interrupts only, the response time to get the vector and force the call.
— 11 state times for an internal stack or 13 for an external stack (assuming a zero-wait-
state bus)
5.4.2.1 Standard Interrupt Latency
The worst-case delay for a standard interrupt is 56 state times (4 + 39 + 11 + 2) if the stack is in
external memory (Figure 5-4). This delay time does not include the time needed to execute the
first instruction in the interrupt service routine or to execute the instruction following a protected
instruction.