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8XC196MC, MD, MH USER’S MANUAL
11-14
The maximum output frequency depends upon the total interrupt latency and the interrupt-service
execution times used by your system. As additional EPA channels and the other functions of the
microcontroller are used, the maximum PWM frequency decreases because the total interrupt la-
tency and interrupt-service execution time increases. To determine the maximum, low-speed
PWM frequency in your system, calculate your system's worst-case interrupt latency and worst-
case interrupt-service execution time, and then add them together. The worst-case interrupt la-
tency is the total latency of all the interrupts (both normal and PTS) used in your system. The
worst-case interrupt-service execution time is the total execution time of all interrupt service rou-
tines and PTS routines.
Assume a system with a single EPA channel, a single enabled interrupt, and the following inter-
rupt service routine.
;If EPA0-
x
interrupt is generated
EPA0-
x
_ISR:
PUSHA
LD EPA
x
_CON, #toggle_command
ADD EPA
x
_TIME, TIMER
x
, [next_duty_ptr]; Load next event time
POPA
RET
The worst-case interrupt latency for a single-interrupt system is 56 state times for external stack
usage and 54 state times for internal stack usage (see “Standard Interrupt Latency” on page 5-10).
To determine the execution time for an interrupt service routine, add up the execution time of the
instructions (Table A-9).
The total execution time for the ISR that services the EPA interrupts is 79 state times for external
stack usage or 71 state times for internal stack usage. Therefore, a single capture/compare channel
can be updated every 125 state times assuming internal stack usage (54 + 71). Each PWM period
requires two updates (one setting and one clearing), so the execution time for a PWM period
equals 250 state times. When the input frequency on XTAL1 is 16 MHz, the PWM period is 31.25
µs and the maximum PWM frequency is 32 kHz.
11.4.2.2 Generating the Highest-speed PWM Output
You can generate a highest-speed, pulse-width modulated output with a pair of EPA channels and
a dedicated timer/counter. The first channel toggles the output when the timer value matches
EPAx_TIME, and at some later time, the second channel toggles the output again and resets the
timer/counter. This restarts the cycle. No interrupts are required, resulting in the highest possible
speed. Software must calculate and load the appropriate EPAx_TIME values and load them at the
correct time in the cycle in order to change the frequency or duty cycle.