Filter
Top Products
14-7
SPECIAL OPERATING MODES
14.4.3.3 Asserting the External Interrupt Signal
The final way to exit powerdown mode is to assert the external interrupt signal (EXTINT) for at
least 50 ns. Although EXTINT is normally a sampled input, the powerdown circuitry uses it as a
level-sensitive input. The interrupt need not be enabled to bring the device out of powerdown, but
the pin must be configured as a special-function input (see “Bidirectional Port Pin Configura-
tions” on page 6-9). Figure 14-2 shows the power-up and power-down sequence when using an
external interrupt to exit powerdown.
When an external interrupt brings the device out of powerdown mode, the corresponding pending
bit is set in the interrupt pending register. If the interrupt is enabled, the device executes the in-
terrupt service routine, then fetches and executes the instruction following the IDLPD #2 instruc-
tion. If the interrupt is disabled (masked), the device fetches and executes the instruction
following the IDLPD #2 instruction and the pending bit remains set until the interrupt is serviced
or software clears the pending bit.
Figure 14-2. Power-up and Power-down Sequence When Using an External Interrupt
When using an external interrupt signal to exit powerdown mode, we recommend that you con-
nect the external RC circuit shown in Figure 14-3 to the V
PP
pin. The discharging of the capacitor
causes a delay that allows the oscillator to stabilize before the internal CPU and peripheral clocks
are enabled.
XTAL1
CLKOUT
PH1
Internal Powerdown
Signal
EXTINT
V
PP
Timeout
(Internal)
A0078-01