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5-9
STANDARD AND PTS INTERRUPTS
5.3.4 End-of-PTS Interrupts
When the PTSCOUNT register decrements to zero at the end of a single transfer, block transfer,
A/D scan, or serial I/O routine, hardware clears the corresponding bit in the PTSSEL register,
(Figure 5-6 on page 5-14) which disables PTS service for that interrupt. It also sets the corre-
sponding PTSSRV bit, requesting an end-of-PTS interrupt. An end-of-PTS interrupt has the same
priority as a corresponding standard interrupt. The interrupt controller processes it with an inter-
rupt service routine that is stored in the memory location pointed to by the standard interrupt vec-
tor. For example, the PTS services the EPA0 interrupt if PTSSEL.2 is set. The interrupt vectors
through 2044H, but the corresponding end-of-PTS interrupt vectors through 2004H, the standard
EPA0 interrupt vector. When the end-of-PTS interrupt vectors to the interrupt service routine,
hardware clears the PTSSRV bit. The end-of-PTS interrupt service routine should reinitialize the
PTSCB, if required, and set the appropriate PTSSEL bit to re-enable PTS interrupt service.
5.4 INTERRUPT LATENCY
Interrupt latency is the total delay between the time that the interrupt request is generated (not
acknowledged) and the time that the device begins executing either the standard interrupt service
routine or the PTS interrupt service routine. A delay occurs between the time that the interrupt
request is detected and the time that it is acknowledged. An interrupt request is acknowledged
when the current instruction finishes executing. If the interrupt request occurs during one of the
last four state times of the instruction, it may not be acknowledged until after the next instruction
finishes. This additional delay occurs because instructions are prefetched and prepared a few state
times before they are executed. Thus, the maximum delay between interrupt request and ac-
knowledgment is four state times plus the execution time of the next instruction.
When a standard interrupt request is acknowledged, the hardware clears the interrupt pending bit
and forces a call to the address contained in the corresponding interrupt vector. When a PTS in-
terrupt request is acknowledged, the hardware immediately vectors to the PTSCB and begins ex-
ecuting the PTS routine.
5.4.1 Situations that Increase Interrupt Latency
If an interrupt request occurs while any of the following instructions are executing, the interrupt
will not be acknowledged until after the next instruction is executed:
• the signed prefix opcode (FE) for the two-byte, signed multiply and divide instructions
• any of these eight protected instructions: DI, EI, DPTS, EPTS, POPA, POPF, PUSHA,
PUSHF (see Appendix A for descriptions of these instructions)
• any of the read-modify-write instructions: AND, ANDB, OR, ORB, XOR, XORB
Both the unimplemented opcode interrupt and the software trap interrupt prevent other interrupt
requests from being acknowledged until after the next instruction is executed.