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Index-7
INDEX
ORB instruction, A-2, A-28, A-43, A-48, A-53
Oscillator
and powerdown mode, 14-5
external crystal, 13-6
on-chip, 13-5
OTPROM
controlling access to internal memory,
16-3–16-6
controlling fetches from external memory,
16-6–16-7
memory map, 16-2
programming, 16-1–16-33
See also programming modes
ROM-dump mode, 16-30
verifying, 16-30
Overflow (V) flag, A-4, A-5, A-21, A-22
Overflow-trap (VT) flag, A-4, A-5, A-11, A-22,
A-23
P
P0.7:0, B-17
P0.7:4
and programming modes, 16-14
P0_PIN, C-69
P1.3:0, B-17
P1.7:0, B-17
P1_DIR, C-69
P1_MODE, C-69
P1_PIN, C-69
P1_REG, C-69
P2.2 considerations, 14-7
P2.7:0, B-18
P2_DIR, C-69
P2_MODE, C-69
P2_PIN, C-69
P2_REG, C-69
P3.7:0, B-18
P4.7:0, B-18
P5.0–P5.7
See also port 5
P5.7:0, B-18
P5_PIN
SFRs, 6-6
P6.7:0, B-18
P6_DIR, C-69
P6_MODE, C-69
P6_PIN, C-69
P6_REG, C-69
P7.7:0, B-19
PACT#, B-19
PALE#, 16-8, 16-10, 16-11, B-19
Parameters, passing to subroutines, 3-10
Parity, 7-7, 7-8, 7-9
PBUS, 16-12
PBUS15:0, B-19
PC (program counter), 2-4
master, 2-6
slave, 2-6
Peripheral Interrupt mask register, 5-17, C-35
Peripheral interrupt pending register, 5-23, C-37
Peripherals, internal, 2-8
Phase compare register, 9-17, C-59
Pin-out diagrams, B-3, B-4, B-5, B-7, B-8, B-11,
B-12
PLM-96
conventions, 3-9, 3-10, 3-11
interrupt procedures, 3-11
PMODE, 16-11, 16-13
and programming modes, 16-14
PMODE3:0, B-19
POP instruction, A-3, A-29, A-45, A-49, A-54
POPA instruction, A-2, A-29, A-46, A-49, A-54
POPF instruction, A-2, A-29, A-46, A-49, A-54
Port 0, 6-2, B-17
considerations, 6-4, 12-13, 13-5
idle, powerdown, reset status, B-25
input only pins, 6-2
overview, 6-1
structure, 6-3
Port 1, 6-2, B-17
considerations, 6-4, 6-12
idle, powerdown, reset status, B-23, B-25
input buffer, 6-7
input only pins, 6-2
logic tables, 6-9
operation, 6-4
overview, 6-1
SFRs, 6-6, 14-3
Port 2, 14-2, B-18
considerations, 6-12
idle, powerdown, reset status, B-23, B-25
operation, 6-4
overview, 6-1
P2.7 considerations, 6-12
P2.7 reset status, 6-7