Filter
Top Products
8XC196MC, MD, MH USER’S MANUAL
C-36
PI_MASK
0 OVRTM1 Timer 1 Overflow/Underflow
Setting this bit enables the timer 1 overflow/underflow interrupt.
The timer 1 and timer 2 overflow/underflow interrupts are associated with
the overflow/underflow timer interrupt (OVRTM). Setting INT_MASK.0
enables OVRTM.
PI_MASK (Continued)
Address:
Reset State:
1FBCH
AAH
The peripheral interrupt mask (PI_MASK) register enables or disables (masks) interrupt requests
associated with the peripheral interrupt (PI), the serial port interrupt (SPI), and the overflow/underflow
timer interrupt (OVRTM).
7 0
8XC196MC
———WG —OVRTM2 — OVRTM1
7 0
8XC196MD
— COMP5 —WG —OVRTM2 — OVRTM1
7 0
8XC196MH
—SP1—SP0 —OVRTM2 — OVRTM1
Bit
Number
Bit
Mnemonic
Function