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CONTENTS
FIGURES
Figure Page
7-5 Serial Port Frames in Mode 2 and 3.............................................................................7-9
7-6 Serial Port Control (SP
x
_CON) Register....................................................................7-10
7-7 Serial Port
x
Baud Rate (SP
x
_BAUD) Register.........................................................7-12
7-8 Serial Port Status
(SP
x
_STATUS) Register...............................................................7-15
8-1 Frequency Generator Block Diagram...........................................................................8-1
8-2 Frequency (FREQ_GEN) Register...............................................................................8-3
8-3 Frequency Generator Count (FREQ_CNT) Register....................................................8-4
8-4 Infrared Remote Control Application Block Diagram....................................................8-5
8-5 Data Encoding Example...............................................................................................8-5
9-1 Waveform Generator Block Diagram............................................................................9-2
9-2 Dead-time Generator Circuitry......................................................................................9-5
9-3 Protection Circuitry .......................................................................................................9-6
9-4 Center-aligned Modes — Counter Operation...............................................................9-9
9-5 Center-aligned Modes — Output Operation...............................................................9-10
9-6 Edge-aligned Modes — Counter Operation ...............................................................9-11
9-7 Edge-aligned Modes — Output Operation .................................................................9-11
9-8 WG Output Configuration (WG_OUTPUT) Register ..................................................9-13
9-9 Waveform Generator Protection (WG_PROTECT) Register......................................9-15
9-10 Waveform Generator Reload (WG_RELOAD) Register.............................................9-16
9-11 Phase Compare (WG_COMP
x
) Register...................................................................9-17
9-12 Waveform Generator Control (WG_CONTROL) Register..........................................9-18
9-13 Waveform Generator Counter (WG_COUNTER) Register ........................................9-19
9-14 Effect of Dead Time on Duty Cycle ............................................................................9-20
10-1 PWM Block Diagram ..................................................................................................10-2
10-2 PWM Output Waveforms............................................................................................10-4
10-3 PWM Period (PWM_PERIOD) Register.....................................................................10-6
10-4 PWM Control (PWM
x
_CONTROL) Register ..............................................................10-7
10-5 PWM Count (PWM_COUNT) Register.......................................................................10-8
10-6 Waveform Generator Output Configuration (WG_OUTPUT) Register.......................10-9
10-7 D/A Buffer Block Diagram.........................................................................................10-10
10-8 PWM to Analog Conversion Circuitry .......................................................................10-10
11-1 EPA Block Diagram....................................................................................................11-2
11-2 EPA Timer/Counters ..................................................................................................11-6
11-3 Quadrature Mode Interface ........................................................................................11-8
11-4 Quadrature Mode Timing and Count..........................................................................11-9
11-5 A Single EPA Capture/Compare Channel................................................................11-10
11-6 EPA Simplified Input-capture Structure....................................................................11-11
11-7 Valid EPA Input Events ............................................................................................11-11
11-8 Timer 1 Control (T1CONTROL) Register .................................................................11-16
11-9 Timer 2 Control (T2CONTROL) Register .................................................................11-17
11-10 EPA Control (EPA
x
_CON) Registers .......................................................................11-19
11-11 EPA Compare Control (COMP
x
_CON) Registers....................................................11-22
12-1 A/D Converter Block Diagram ....................................................................................12-1
12-2 A/D Test (AD_TEST) Register....................................................................................12-5