Filter
Top Products
10-7
PULSE-WIDTH MODULATOR
10.5.1 Sample Calculations
For example, assume that F
XTAL
1
equals 16 MHz and the value written to the PWM_PERIOD reg-
ister is FFH, thus the desired period of the PWM output waveform is 8.19 ms. If
PWMx_CONTROL equals 8AH (138 decimal), the pulsewidth is held high for 4.42 ms (and low
for 3.77 ms) of the total 8.19 ms period, resulting in a duty cycle of approximately 54%.
10.5.2 Reading the Current Value of the Down-counter
You can read the PWM_COUNT register to find the current value of the down-counter (see Fig-
ure 10-5).
PWM
x
_CONTROL
x
= 0–1
Address:
Reset State:
Table 10-2 on page
10-3
00H
The PWM control (PWM
x
_CONTROL) register determines the duty cycle of the PWM
x
channel. A
zero loaded into this register causes the PWM to output a low continuously (0% duty cycle). An FFH in
this register causes the PWM to have its maximum duty cycle (99.6% duty cycle).
7 0
PWM Duty Cycle
Bit
Number
Function
7:0 PWM Duty Cycle
This register controls the PWM duty cycle. A zero loaded into this register causes the
PWM to output a low continuously (0% duty cycle). An FFH in this register causes the
PWM to have its maximum duty cycle (99.6% duty cycle).
Figure 10-4. PWM Control (PWM
x
_CONTROL) Register