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14-3
SPECIAL OPERATING MODES
14.2 REDUCING POWER CONSUMPTION
Both power-saving modes conserve power by disabling portions of the internal clock circuitry
(Figure 14-1). The following paragraphs describe both modes in detail.
P1_DIR (MH)
P2_DIR
P5_DIR
P7_DIR (MD)
1F9BH
1FD2H
1FF3H
1FD3H
Port
x
Direction
Each bit of P
x
_DIR controls the direction of the corresponding pin.
Clearing a bit configures a pin as a complementary output; setting
a bit configures a pin as an input or open-drain output. (Open-
drain outputs require external pull-ups.)
P1_MODE(MH)
P2_MODE
P5_MODE
P7_MODE(MD)
1F99H
1FD0H
1FF1H
1FD1H
Port
x
Mode
Each bit of P
x
_MODE controls whether the corresponding pin
functions as a standard I/O port pin or as a special-function
signal. Setting a bit configures a pin as a special-function signal;
clearing a bit configures a pin as a standard I/O port pin.
P1_REG (MH)
P2_REG
P5_REG
P7_REG (MD)
1F9DH
1FD4H
1FF5H
1FD5H
Port
x
Data Output
For an input, set the corresponding P
x
_REG bit.
For an output, write the data to be driven out by each pin to the
corresponding bit of P
x
_REG. When a pin is configured as
standard I/O (P
x
_MODE.
y
= 0), the result of a CPU write to
P
x
_REG is immediately visible on the pin. When a pin is
configured as a special-function signal (P
x
_MODE.
y
= 1), the
associated on-chip peripheral or off-chip component controls the
pin. The CPU can still write to P
x
_REG, but the pin is unaffected
until it is switched back to its standard I/O function.
This feature allows software to configure a pin as standard I/O
(clear P
x
_MODE.
y
), initialize or overwrite the pin value, then
configure the pin as a special-function signal (set P
x
_MODE.
y
). In
this way, initialization, fault recovery, exception handling, etc., can
be done without changing the operation of the associated
peripheral.
Table 14-2. Operating Mode Control and Status Registers (Continued)
Mnemonic Address Description