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Interrupt Control Unit
8-6
8.1.4 Software Exceptions, Traps, and NMI
The following predefined interrupts cannot be masked by programming.
8.1.4.1 Divide Error Exception (Interrupt Type 00h)
Generated when a DIV or IDIV instruction quotient cannot be expressed in the number of
destination bits.
8.1.4.2 Trace Interrupt (Interrupt Type 01h)
If the trace flag (TF) in the Processor Status Flags Register is set, the trace interrupt is
generated after most instructions. This interrupt allows programs to execute in single-step
mode. The interrupt is not generated after prefix instructions like REP, instructions that
modify segment registers like POP DS, or the WAIT instruction.
Taking the trace interrupt clears the TF bit after the processor status flags are pushed onto
the stack. The IRET instruction at the end of the single step interrupt service routine restores
the processor status flags (and the TF bit) and transfers control to the next instruction to
be traced.
Trace mode is initiated by pushing the processor status flags onto the stack, setting the TF
flag on the stack, and then popping the flags.
8.1.4.3 Nonmaskable Interrupt—NMI (Interrupt Type 02h)
This pin indicates to the microcontroller that an interrupt request has occurred. The NMI
signal is the highest priority hardware interrupt and, unlike the INT4–INT0 pins, cannot be
masked. The microcontroller always transfers program execution to the location specified
by the nonmaskable interrupt vector in the microcontroller interrupt vector table when NMI
is asserted.
A Low to High transition is required to assert NMI. Pulling the pin High during reset has no
effect on program execution.
Although NMI is the highest priority interrupt source, it does not participate in the priority
resolution process of the maskable interrupts. There is no bit associated with NMI in the
interrupt in-service or interrupt request registers. This means that a new NMI request can
interrupt an executing NMI interrupt service routine. As with all hardware interrupts, the IF
(interrupt flag) is cleared when the processor takes the interrupt, disabling the maskable
interrupt sources. However, if maskable interrupts are re-enabled by software in the NMI
interrupt service routine, via the STI instruction for example, the fact that an NMI is currently
in service does not have any effect on the priority resolution of maskable interrupt requests.
For this reason, it is strongly advised that the interrupt service routine for NMI not enable
the maskable interrupts.