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System Overview
3-8
executing NMI interrupt service routine. As with all hardware interrupts,
the IF (interrupt flag) is cleared when the processor takes the interrupt,
disabling the maskable interrupt sources. However, if maskable
interrupts are re-enabled by software in the NMI interrupt service routine
(via the STI instruction for example), the fact that an NMI is currently in
service will not have any effect on the priority resolution of maskable
interrupt requests. For this reason, it is strongly advised that the interrupt
service routine for NMI does not enable the maskable interrupts.
An NMI transition from Low to High is latched and synchronized
internally, and it initiates the interrupt at the next instruction boundary.
To guarantee that the interrupt is recognized, the NMI pin must be
asserted for at least one CLKOUTA period. Because NMI is rising edge
sensitive, holding the pin High during reset has no effect on program
execution.
PCS
3–PCS0 Peripheral Chip Selects (output, synchronous)
These pins indicate to the system that a memory access is in progress
to the corresponding region of the peripheral memory block (either I/O
or memory address space). The base address of the peripheral memory
block is programmable. PCS
3–PCS0 are held High during a bus hold
or reset condition.
Unlike the UCS
and LCS chip selects, the PCS outputs assert with the
multiplexed AD address bus.
Note: PCS
4 is not available on the Am186ER and Am188ER
microcontrollers. Note also that each peripheral chip select asserts over
a 256-byte address range, which is twice the address range covered by
peripheral chip selects in the 80C186 and 80C188 microcontrollers.
PCS
5/A1 Peripheral Chip Select 5 (output, synchronous)
Latched Address Bit 1 (output, synchronous)
PCS
5—This pin indicates to the system that a memory access is in
progress to the sixth region of the peripheral memory block (either I/O
or memory address space). The base address of the peripheral memory
block is programmable. PCS
5 is held High during a bus hold or reset
condition. It is also held High during reset.
Note: Unlike the UCS
and LCS chip selects, the PCS outputs assert
with the multiplexed AD address bus. Note also that each peripheral
chip select asserts over a 256-byte address range, which is twice the
address range covered by peripheral chip selects in the 80C186 and
80C188 microcontrollers.
A1—When the EX bit in the MCS
and PCS Auxiliary Register is 0, this
pin supplies an internally latched address bit 1 to the system. During a
bus hold condition, A1 retains its previously latched value.
PCS
6/A2 Peripheral Chip Select 6 (output, synchronous)
Latched Address Bit 2 (output, synchronous)
PCS
6—This pin indicates to the system that a memory access is in
progress to the seventh region of the peripheral memory block (either
I/O or memory address space). The base address of the peripheral
memory block is programmable. PCS
6 is held High during a bus hold
or reset condition.