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Index I-3
ZF (Zero Flag), 2-3
Block diagram, 1-4–1-5
BRK bit (Send Break), 11-2
BRKI bit (Break Interrupt), 11-4
BRKVAL bit (Break Value), 11-2
Bus
interface unit, 3-21
nonmultiplexed address, 3-21
operation, 3-18
read and write timing, 3-19–3-20
Byte write enables, 3-21
C
C bit (Cascade Mode), 8-14
CAD bit (CLKOUTA Drive Disable)
System Configuration Register, 4-7
CAF bit (CLKOUTA Output Frequency)
System Configuration Register, 4-7
Carry Flag bit, 2-3
Cascade mode, 8-11
Catalog, xiv
CBD bit (CLKOUTB Drive Disable)
System Configuration Register, 4-7
CBF bit (CLKOUTB Output Frequency)
System Configuration Register, 4-7
CD-ROM documentation, xiv
CF bit (Carry Flag)
Processor Status Flags Register, 2-3
Characteristics, 1-2
CHG bit (Change Start Bit), 10-4
Chip select timing, 5-2
CLKOUTA signal (Clock Output A)
definition, 3-4
use, 3-25
CLKOUTB signal (Clock Output B)
definition, 3-4
use, 3-25
CLKSEL1 signal (Clock Select 1), 3-13
CLKSEL2 signal (Clock Select 2), 3-15
Clock
and power management unit, 3-23
frequency, 3-23
generation, 1-6
prescaler register, 7-2
source, 3-24
Clocking modes, 3-16
Code Segment (CS) Register, 2-8
CONT bit (Continuous Mode Bit)
Timer 0 Mode/Control Register, 9-4
Timer 1 Mode/Control Register, 9-4
Timer 2 Mode/Control Register, 9-5
Crystal-driven clock source, 3-24
D
D1-D0 field (DMA Channel Interrupt In-Service), 8-23,
8-33, 8-35
D1-D0 field (DMA Channel Interrupt Masks), 8-25
D1-D0 field (DMA Channel Interrupt Request), 8-22, 8-
32
DA field (Address Disable)
Upper Memory Chip Select Register, 5-5, 5-7
Data Segment (DS) Register, 2-8
Data sheet, xiv
Data types, 2-8
DDA15-DDA0 field (DMA Destination Address Low),
10-7
DDA19-DDA16 field (DMA Destination Address High),
10-6
DDEC bit (Destination Decrement), 10-3
DE0 bit (SDEN0 Enable), 12-4
DE1 bit (SDEN1 Enable), 12-4
DEN signal (Data Enable), 3-4
Development
support, 1-8
third-party products, xiv
tools, xiv
DF bit (Direction Flag)
Processor Status Flags Register, 2-2
DHLT bit (DMA Halt), 8-21, 8-31
DINC bit (Destination Increment), 10-3
Direct mode addressing, 2-10
Direction Flag bit, 2-2
Displacement, Based Indexed mode, 2-10
Distinctive characteristics, 1-2
Divide by Two mode, 3-23
DM/IO bit (Destination Address Space Select), 10-3
DMA
operation, 10-1
requests, 10-10
timing, 10-11
transfer rates, 10-10
unit block diagram, 10-2
DMA 0 Control Register, 10-3
DMA 0 Destination Address High Register, 10-6
DMA 0 Destination Address Low Register, 10-7
DMA 0 Interrupt Control Register
Master mode, 8-18
Slave mode, 8-30
DMA 0 Source Address High Register, 10-8
DMA 0 Source Address Low Register, 10-9
DMA 0 Transfer Count Register, 10-5
DMA 1 Control Register, 10-3