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Asynchronous Serial Port
11-2
11.2.1 Serial Port Control Register (SPCT, Offset 80h)
The Serial Port Control register controls both the transmit and receive sections of the serial
port. The format of the Serial Port Control register is shown in Figure 11-1.
Figure 11-1 Serial Port Control Register (SPCT, offset 80h)
The value of SPCT at reset is 0000h.
Bits 15–12: Reserved—Set to 0.
Bit 11: Transmit Holding Register Empty Interrupt Enable (TXIE)—This bit enables the
serial port to generate an interrupt for the transmit holding register empty condition,
indicating that the serial port is ready to accept a new character for transmission. If this bit
is 1 and the Serial Port Transmit Holding register does not contain valid data, the serial
port generates an interrupt request. The value of TXIE after power-on reset is 0.
Bit 10: Receive Data Ready Interrupt Enable (RXIE)—This bit enables the serial port to
generate an interrupt for the receive data ready condition. If this bit is 1 and the Serial Port
Receive Buffer register contains data that has been received on the serial port, the serial
port generates an interrupt request. The value of RXIE after power-on reset is 0.
Bit 9: Loopback (LOOP)—Setting this bit to 1 places the serial port in the loopback mode.
In this mode, the TXD output is set High and the transmit shift register is connected to the
receive shift register. Data transmitted by the transmit section is immediately received by
the receive section. The loopback mode is provided for testing the serial port. The value of
LOOP after power-on reset is 0.
Bit 8: Send Break (BRK)—Setting this bit to 1 causes the serial port to send a continuous
level on the TXD output. A break is a continuous Low on the TXD output for a duration of
more than one frame transmission time. The level driven on the TXD output is determined
by the BRKVAL bit.
To use the transmitter to time the frame, set the BRK bit when the transmitter is empty
(indicated by the TEMT bit of the Serial Port Status register), write the serial port transmit
holding register, then wait until the TEMT bit is again set before resetting the BRK bit.
Because the TXD output is held constant while BRK is set, the data written to the transmit
holding register will not appear on the pin. The value of BRK after power-on reset is 0.
Bit 7: Break Value (BRKVAL)—This bit determines the output value transmitted on the
TXD pin during a send break operation. If BRKVAL is 1, a continuous High level is driven
on the TXD output. If BRKVAL is 0, a continuous Low level is driven on the TXD output.
Only a continuous Low value (BRKVAL=0) will result in a break being detected by the
receiver. The value of BRKVAL after power-on reset is 0.
15
70
Reserved
TXIE
RXIE
LOOP
BRK
PMODE
BRKVAL
RMODE
RSIE
TMODE
STP
WLGN