Filter
Top Products
I-6 Index
Midrange Memory Chip Select Register, 5-8
MS bit (Memory/I/O Space Selector), 5-11
MSK bit (Interrupt Mask)
description, 8-2
DMA Interrupt Control Registers, 8-18
Timer Interrupt Control Registers, 8-18
MSK bit (Mask)
DMA Interrupt Control Registers, 8-30
INT0 Control Register, 8-14
INT1 Control Register, 8-14
INT2 Control Register, 8-16
INT3 Control Register, 8-16
INT4 Control Register, 8-17
Serial Port Interrupt Control Register, 8-20
Timer Interrupt Control Registers, 8-30
Watchdog Timer Interrupt Control Register, 8-19
N
NMI signal (Nonmaskable Interrupt), 3-7
Nonmaskable interrupts, 8-2, 8-6
Nonmultiplexed address bus, 3-21
NSPEC bit (Non-Specific EOI), 8-28
O
OER bit (Overrun Error), 11-4
OF bit (Overflow Flag)
Processor Status Flags Register, 2-2
Offset calculation, 2-10
ONCE0 signal (ONCE Mode Request 0), 3-7
ONCE1 signal (ONCE Mode Request 1), 3-15
On-line documentation, xiv
Ordinal data type, 2-8
Overflow Flag bit, 2-2
Overlap, chip select, 5-2
P
P bit (Prescaler Bit)
Timer 0 Mode/Control Register, 9-3
Timer 1 Mode/Control Register, 9-3
P bit (Relative Priority), 10-4
Packed BCD data type, 2-8
Parity Flag bit, 2-3
PB bit (SSI Port Busy), 12-3
PCS and MCS Auxiliary Register, 5-10
PCS3-PCS0 signals (Peripheral Chip Selects 3-0), 3-8
PCS5 signal (Peripheral Chip Select 5), 3-8
PCS6 signal (Peripheral Chip Select 6), 3-8
PDATA15-PDATA0 field (PIO Data BIts), 13-5
PDATA31-PDATA16 field (PIO Data BIts), 13-5
PDIR15-PDIR0 field (PIO Direction Bits), 13-4
PDIR31-PDIR16 field (PIO Direction Bits), 13-4
PER bit (Parity Error), 11-4
Peripheral Chip Select Register, 5-12
Peripheral Control Block Relocation Register, 4-4
PF bit (Parity Flag)
Processor Status Flags Register, 2-3
Phase-locked loop (PLL), 3-23
Physical address generation, 2-4
Physical dimensions, xiv
Pin Descriptions, 3-1
Pins used by emulators, 3-17
PIO Data 0 Register, 13-5
PIO Data 1 Register, 13-5
PIO Direction 0 Register, 13-4
PIO Direction 1 Register, 13-4
PIO Mode 0 Register, 13-3
PIO Mode 1 Register, 13-3
PIO pullup/pulldown resistor, 13-3
PIO31-PIO0 signals (Programmable I/O Pins 31-0), 3-9
PMODE field (Parity Mode), 11-3
PMODE15-PMODE0 field (PIO Mode Bits), 13-3
PMODE31-PMODE16 field (PIO Mode Bits), 13-3
Pointer data type, 2-9
Poll Register
Master mode, 8-27
Poll Status Register
Master mode, 8-26
Polled interrupts, 8-12
Power management unit, 3-23
Power-Save Control Register, 4-7
Power-save operation, 3-25
PR2-PR0 field (Priority Level)
DMA Interrupt Control Register, 8-30
Timer Interrupt Control Register, 8-30
PR2-PR0 field (Priority)
DMA Interrupt Control Registers, 8-18
INT0 Control Register, 8-15
INT1 Control Register, 8-15
INT2 Control Register, 8-16
INT3 Control Register, 8-16
INT4 Control Register, 8-17
Serial Port Interrupt Control Register, 8-20
Timer Interrupt Control Registers, 8-18
Watchdog Timer Interrupt Control Register, 8-19
Priority Mask Register
Master mode, 8-24
Slave mode, 8-34
PRM2-PRM0 field (Priority Field Mask), 8-24, 8-34
Processor Release Level Register, 4-6