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Register Summary
A-5
Figure A-1 Internal Register Summary (continued)
15 7 0
M6–M0
RA19 RA13
0
Memory Partition Register (MDRAM)
Page 7-1
E0
15 7 0
TC15–TC0
DMA 1 Transfer Count Register (D1TC)
Page 10-5
D8
15 7 0
DDA15–DDA0
DMA 1 Destination Address Low Register (D1DSTL)
Page 10-7
D4
15
70
Reserved
DSA19–DSA16
DMA 1 Source Address High Register (D1SRCH)
Page 10-8
D2
15
70
DSA15–DSA0
DMA 1 Source Address Low Register (D1SRCL)
Page 10-9
D0
15 7 0
Reserved
DDA19–DDA16
DMA 1 Destination Address High Register (D1DSTH)
Page 10-6
D6
15 7 0
DINC
DDEC
SM/IO
SINC
SDEC
B
/WSTCHGResTC INT SYN P
TDRQ
DMA 1 Control Register (D1CON)
Page 10-3
DA
DM/IO
00000000