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System Overview
3-12
RD Read Strobe (output, synchronous, three-state)
RD
—This pin indicates to the system that the microcontroller is
performing a memory or I/O read cycle. RD
is guaranteed not to be
asserted before the address and data bus is three-stated during the
address-to-data transition. RD
is three-stated during bus holds and
ONCE mode.
RES
Reset (input, asynchronous, level-sensitive)
This pin causes the microcontroller to perform a reset. When RES
is
asserted, the microcontroller immediately terminates its present activity,
clears its internal logic, and CPU control is transferred to the reset
address FFFF0h.
RES
must be held Low for at least 1 ms. The assertion of RES can be
asynchronous to CLKOUTA because RES
is synchronized internally.
For proper initialization, V
CC
must be within specifications, and
CLKOUTA must be stable for more than four CLKOUTA periods during
which RES
is asserted.
The microcontroller begins fetching instructions approximately
6.5 CLKOUTA periods after RES
is deasserted. This input is provided
with a Schmitt trigger to facilitate power-on RES
generation via an RC
network.
RFSH
2/ADEN Refresh 2 (three-state, output, synchronous)
Address Enable (input, internal pullup)
RFSH
2—Available on the Am188ER microcontroller only, RFSH2/
ADEN
is asserted Low to signify a DRAM refresh bus cycle. The use
of RFSH
2/ADEN to signal a refresh is not valid when PSRAM mode is
selected. Instead, the MCS
3/RFSH signal is provided to the PSRAM.
During reset, this pin is a pullup. This pin is three-stated during bus
holds and ONCE mode.
ADEN
—If RFSH2/ADEN is held High or left floating on power-on reset,
the AD bus (AO15–AO8 and AD7–AD0) is enabled or disabled during
the address portion of LCS
and UCS bus cycles based on the DA bit in
the LMCS and UMCS registers. If the DA bit is set, the memory address
is accessed on the A19–A0 pins. This mode of operation reduces power
consumption. There is a weak internal pullup resistor on RFSH
2/ADEN,
so no external pullup is required.
If RFSH
2/ADEN is held Low on power-on reset, the AD bus drives both
addresses and data. (S6 and UZI also assume their normal functionality
in this instance. See Table 3-1 on page 3-10.) The pin is sampled within
three crystal clock cycles after the rising edge of RES
. RFSH2/ADEN is
three-stated during bus holds and ONCE mode.
See section 5.5.1 and section 5.5.2 for additional information on
enabling and disabling the AD bus during the address phase of a bus
cycle.
RXD Receive Data (input, asynchronous)
This pin supplies asynchronous serial receive data from the system to
the internal UART of the microcontroller.