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DMA Controller
10-5
10.3.2 DMA Transfer Count Registers (D0TC, Offset C8h, D1TC,
Offset D8h)
Each DMA channel maintains a 16-bit DMA Transfer Count register (DTC). This register
is decremented after every DMA cycle, regardless of the state of the TC bit in the DMA
Control register. However, if the TC bit in the DMA control word is set or if unsynchronized
transfers are programmed, DMA activity terminates when the Transfer Count register
reaches 0.
Figure 10-3 DMA Transfer Count Registers (D0TC, D1TC, offsets C8h and D8h)
The value of D0TC and D1TC at reset is undefined.
Bits 15–0: DMA Transfer Count (TC15–TC0)—Contains the transfer count for a DMA
channel. Value is decremented by 1 after each transfer.
15
70
TC15–TC0