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Interrupt Control Unit
8-26
8.3.12 Poll Status Register (POLLST, Offset 26h)
(Master Mode)
The Poll Status (POLLST) Register mirrors the current state of the Poll Register. The
POLLST Register can be read without affecting the current interrupt request. But when the
Poll Register is read, the current interrupt is acknowledged and the next interrupt takes its
place in the Poll Register.
Figure 8-15 Poll Status Register (POLLST, offset 26h)
Bit 15: Interrupt Request (IREQ)—Set to 1 if an interrupt is pending. When this bit is set
to 1, the S4–S0 field contains valid data.
Bits 14–5: Reserved—Set to 0.
Bits 4–0: Poll Status (S4–S0)—Indicates the interrupt type of the highest priority pending
interrupt.
15
70
S4–S0
IREQ
Reserved