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Interrupt Control Unit
8-16
8.3.2 INT2 and INT3 Control Registers
(I2CON, Offset 3Ch, I3CON, Offset 3Eh)
(Master Mode)
The INT2 interrupt is assigned to interrupt type OEh. The INT3 interrupt is assigned to
interrupt type 0Fh.
The INT2 and INT3 pins can be configured as interrupt acknowledge pins INTA
0 and INTA1
when Cascade mode is implemented.
Figure 8-5 INT2 and INT3 Control Registers (I2CON, I3CON, offsets 3Ch and 3Eh)
The value of I2CON and I3CON at reset is 000Fh.
Bits 15–5: Reserved—Set to 0.
Bit 4: Level-Triggered Mode (LTM)—This bit determines whether the microcontroller
interprets an INT2 or INT3 interrupt request as edge- or level-sensitive. A 1 in this bit
configures INT2 or INT3 as an active High, level-sensitive interrupt. A 0 in this bit configures
INT2 or INT3 as a Low-to-High, edge-triggered interrupt. In either case, INT2 or INT3 must
remain High until it is acknowledged.
Bit 3: Mask (MSK)—This bit determines whether the INT2 or INT3 signal can cause an
interrupt. A 1 in this bit masks this interrupt source, preventing INT2 or INT3 from causing
an interrupt. A 0 in this bit enables INT2 or INT3 interrupts.
This bit is duplicated in the Interrupt Mask Register. See the Interrupt Mask Register in
section 8.3.11 on page 8-25.
Bits 2–0: Priority Level (PR2–PR0)—This field determines the priority of INT2 or INT3
relative to the other interrupt signals, as shown in Table 8-3, “Priority Level,” on page 8-15.
Note: The INT2 pin is multiplexed with PIO 31. To enable the pin to function as an interrupt
or interrupt acknowledge, the PIO mode and PIO direction settings for the INT2 pin must
be set to 0 for normal operation. For more information, see Chapter 13, “Programmable I/
O Pins.”
15
70
Reserved
PR2
PR1
PR0
MSK
LTM