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Chip Select Unit
5-7
Bits 11–8: Reserved—Set to 1.
Bit 7: Disable Address (DA)—The DA bit enables or disables the AD15–AD0 bus during
the address phase of a bus cycle when LCS
is asserted. If DA is set to 1, AD15–AD0 is
not driven during the address phase of a bus cycle when LCS
is asserted. If DA is set to
0, AD15–AD0 is driven during the address phase of a bus cycle. Disabling AD15–AD0
reduces power consumption.
Note: On the Am188ER microcontroller, the AO15–AO8 address pins are driven during
the data phase of the bus cycles, even when the DA bit is set to 1 in either the Upper
Memory Chip Select Register (UMCS) or the Low Memory Chip Select Register (LMCS).
If BHE/ADEN (on the Am186ER) or RFSH2/ADEN (on the Am188ER) is held Low on the
rising edge of RES
, then AD15–AD0 is always driven regardless of the DA setting. This
configures AD15–AD0 to be enabled regardless of the setting of DA.
If BHE
/ADEN (on the Am186ER) or RFSH2/ADEN (on the Am188ER) is High on the rising
edge of RES
, then the DA bit in the UMCS Register and the DA bit in the LMCS Register
control the AD15–AD0 disabling.
See the descriptions of the BHE
/ADEN and RFSH2/ADEN pins in Chapter 3.
Bit 6: PSRAM Mode Enable (PSE)—The PSE bit is used to enable PSRAM support for
the LCS
chip select memory space. When PSE is set to 1, PSRAM support is enabled.
When PSE is set to 0, PSRAM support is disabled. The refresh control unit registers
EDRAM, MDRAM, and CDRAM, must be configured for auto refresh before PSRAM
support is enabled.
Bits 5–3: Reserved—Set to 1.
Bit 2: Ready Mode (R2)—The R2 bit is used to configure the Ready mode for the LCS
chip select. If R2 is set to 0, external ready is required. If R2 is set to 1, external ready is
ignored. In each case, the processor also uses the value of the R1–R0 bits to determine
the number of wait states to insert.
Bits 1–0: Wait-State Value (R1–R0)—The value of R1–R0 determines the number of wait
states inserted into an access to the LCS
memory area. From zero to three wait states can
be inserted (R1–R0 =00b to 11b).