Filter
Top Products
Interrupt Control Unit
8-14
8.3.1 INT0 and INT1 Control Registers
(I0CON, Offset 38h, I1CON, Offset 3Ah)
(Master Mode)
The INT0 interrupt is assigned to interrupt type 0Ch. The INT1 interrupt is assigned to
interrupt type 0Dh.
When Cascade mode is enabled for INT0 by setting the C bit of I0CON to 1, the INT2 pin
becomes INTA
0, the interrupt acknowledge for INT0.
When Cascade mode is enabled for INT1 by setting the C bit of I1CON to 1, the INT3 pin
becomes INTA
1, the interrupt acknowledge for INT1.
When INT0 is the only pin configured in Cascade mode, it must be programmed to a higher
priority than INT1. When INT1 is the only pin configured in Cascade mode, it must be
programmed to a higher priority than any other maskable interrupt.
Figure 8-4 INT0 and INT1 Control Registers (I0CON, I1CON, offsets 38h and 3Ah)
The value of I0CON and I1CON at reset is 000Fh.
Bits 15–7: Reserved—Set to 0.
Bit 6: Special Fully Nested Mode (SFNM)—When set to 1, enables special fully nested
mode.
Bit 5: Cascade Mode (C)—When set to 1, this bit enables Cascade mode.
Bit 4: Level-Triggered Mode (LTM)—This bit determines whether the microcontroller
interprets an INT0 or INT1 interrupt request as edge- or level-sensitive. A 1 in this bit
configures INT0 or INT1 as an active High, level-sensitive interrupt. A 0 in this bit configures
INT0 or INT1 as a Low-to-High, edge-triggered interrupt. In either case, INT0 or INT1 must
remain High until they are acknowledged.
Bit 3: Mask (MSK)—This bit determines whether the INT0 or INT1 signal can cause an
interrupt. A 1 in this bit masks this interrupt source, preventing INT0 or INT1 from causing
an interrupt. A 0 in this bit enables INT0 or INT1 interrupts.
This bit is duplicated in the Interrupt Mask Register. See the Interrupt Mask Register in
section 8.3.11 on page 8-25.
15
70
Reserved
PR2
PR1
PR0
MSK
LTM
C
SFNM