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DMA Controller
10-13
Each DMA register can be modified while the channel is operating. If the CHG bit is set to
0 when the control register is written, the ST bit of the control register will not be modified
by the write. If multiple channel registers are modified, an internally LOCKed string transfer
should be used to prevent a DMA transfer from occurring between updates to the channel
registers.
10.4.5 DMA Channels on Reset
On reset, the state of the DMA channels is as follows:
n The ST bit for each channel is reset.
n Any transfer in progress is aborted.
n The values of the transfer count registers, source address registers, and destination
address registers are undefined.