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I-2 Index
DHLT (DMA Halt), 8-21, 8-31
DINC (Destination Increment), 10-3
DM/IO (Destination Address Space Select), 10-3
DR/DT (Data Receive/Transmit Complete), 12-3
DSA15-DSA0 (DMA Source Address Low), 10-9
DSA19-DSA16 (DMA Source Address High), 10-8
E (Enable RCU), 7-2
EN (Enable Bit), 9-3, 9-5
EX (Pin Selector), 5-11
EXT (External Clock Bit), 9-4
FER (Framing Error), 11-4
I4-I0 (Interrupt In-Service), 8-23
I4-I0 (Interrupt Mask), 8-25
I4-I0 (Interrupt Requests), 8-22
IF (Interrupt-Enable Flag), 2-3
INH (Inhibit Bit), 9-3, 9-5
INT (Interrupt Bit), 9-3, 9-5
INT (Interrupt), 10-4
IREQ (Interrupt Request), 8-26–8-27
L2-L0 (Interrupt Type), 8-36
LB2-LB0 (Lower Boundary), 5-4
LOOP (Loopback), 11-2
LTM (Level-Triggered Mode), 8-14, 8-16–8-17
M/IO (Memory/I/O Space), 4-4
M6-M0 (MCS Block Size), 5-10
M6-M0 (Refresh Base), 7-1
MC (Maximum Count Bit), 9-3, 9-5
MS (Memory/I/O Space Selector), 5-11
MSK (Interrupt Mask), 8-18
MSK (Mask), 8-14, 8-16–8-17, 8-19–8-20, 8-30
NSPEC (Non-Specific EOI), 8-28
OER (Overrun Error), 11-4
OF (Overflow Flag), 2-2
P (Prescaler Bit), 9-3
P (Relative Priority), 10-4
PB (SSI Port Busy), 12-3
PDATA15-PDATA0 (PIO Data BIts), 13-5
PDATA31-PDATA16 (PIO Data BIts), 13-5
PDIR15-PDIR0 (PIO Direction Bits), 13-4
PDIR31-PDIR16 (PIO Direction Bits), 13-4
PER (Parity Error), 11-4
PF (Parity Flag), 2-3
PMODE (Parity Mode), 11-3
PMODE15-PMODE0 (PIO Mode Bits), 13-3
PMODE31-PMODE16 (PIO Mode Bits), 13-3
PR2-PR0 (Priority Level), 8-30
PR2-PR0 (Priority), 8-15–8-20
PRL (Processor Release Level), 4-6
PRM2-PRM0 (Priority Field Mask), 8-24, 8-34
PSE (PSRAM Mode Enable), 5-7
PSEN (Enable Power-Save Mode), 4-7
R19-R8 (Relocation Address Bits), 4-4
R1-R0 (Wait State Value), 5-5, 5-7, 5-9, 5-11, 5-13
R2 (Ready Mode), 5-5, 5-7, 5-9, 5-11, 5-13
R3 (Wait State Value), 5-13
RC (Reset Configuration), 4-5
RC8-RC0 (Refresh Counter Reload Value), 7-2
RDATA (Receive Data), 11-6
RDR (Receive Data Ready), 11-4
RE (Internal Ram Enable), 6-3
RE/TE (Receive/Transmit Error Detect), 12-3
RIU (Register in Use), 9-3
RMODE (Receive Mode), 11-3
RSIE (Receive Status Interrupt Enable), 11-3
RTG (Retrigger Bit), 9-3
RXIE (Receive Data Ready Interrupt Enable), 11-2
S/M (Slave/Master), 4-4
S4-S0 (Poll Status), 8-26–8-27
S4-S0 (Source Interrupt Type), 8-28
SD (Send Data), 12-5
SDEC (Source Decrement), 10-4
SF (Sign Flag), 2-3
SFNM (Special Fully Nested Mode), 8-14
SINC (Source Increment), 10-4
SM/IO (Source Address Space Select), 10-3
SPI (Serial Port Interrupt In-Service), 8-23
SPI (Serial Port Interrupt Mask), 8-25
SPI (Serial Port Interrupt Request), 8-22
SR (Receive Data), 12-6
SR (Show Read), 6-3
ST (Start/Stop DMA Channel), 10-4
STP (Stop Bits), 11-3
SYN1-SYN0 (Synchronization Type), 10-4
T4-T0 (Interrupt Type), 8-37
T8-T0 (Refresh Count), 7-2
TC (Terminal Count), 10-4
TC15-TC0 (Timer Compare Value), 9-7
TC15-TC0 (Timer Count Register), 10-5
TC15-TC0 (Timer Count Value), 9-6
TDATA (Transmit Data), 11-5
TDRQ (Timer Enable/Disable Request), 10-4
TEMT (Transmitter Empty), 11-4
TF (Trace Flag), 2-3
THRE (Transmit Holding Register Empty), 11-4
TMODE (Transmit Mode), 11-3
TMR (Timer Interrupt In-Service), 8-23
TMR (Timer Interrupt Mask), 8-25
TMR (Timer Interrupt Request), 8-22
TMR0 (Timer 0 Interrupt In-Service), 8-33
TMR0 (Timer 0 Interrupt Mask), 8-35
TMR0 (Timer 0 Interrupt Request), 8-32
TMR2-TMR0 (Timer Interrupt Request), 8-21, 8-31
TMR2-TMR1 (Timer 2/Timer 1 Interrupt In-Service),
8-33
TMR2-TMR1 (Timer 2/Timer 1 Interrupt Mask), 8-35
TRM2-TMR1 (Timer2/Timer1 Interrupt Request), 8-
32
TXIE (Transmit Holding Register Empty Interrupt
Enable), 11-2
WD (Virtual Watchdog Timer Interrupt Request), 8-
22
WD (Watchdog Timer Interrupt In-Service), 8-23
WD (Watchdog Timer Interrupt Mask), 8-25
WLGN (Word Length), 11-3