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LIST OF FIGURES
Figure 1-1 Am186ER Microcontroller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-4
Figure 1-2 Am188ER Microcontroller Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-5
Figure 1-3 Basic Functional System Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1-6
Figure 2-1 Register Set . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Figure 2-2 Processor Status Flags Register (FLAGS) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-2
Figure 2-3 Physical Address Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Figure 2-4 Memory and I/O Space . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-4
Figure 2-5 Supported Data Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2-9
Figure 3-1 Am186ER Microcontroller Address Bus—Normal Read
and Write Operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
Figure 3-2 Am186ER Microcontroller—Read and Write with Address Bus Disable
In Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-19
Figure 3-3 Am188ER Microcontroller Address Bus—Normal Read and Write Operation . 3-20
Figure 3-4 Am188ER Microcontroller—Read and Write with Address Bus Disable
In Effect . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-20
Figure 3-5 Oscillator Configurations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-24
Figure 3-6 Clock Organization. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3-25
Figure 4-1 Peripheral Control Block Register Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4-2
Figure 4-2 Peripheral Control Block Relocation Register (RELREG, offset FEh) . . . . . . . . 4-4
Figure 4-3 Reset Configuration Register (RESCON, offset F6h) . . . . . . . . . . . . . . . . . . . . 4-5
Figure 4-4 Processor Release Level Register (PRL, offset F4h). . . . . . . . . . . . . . . . . . . . . 4-6
Figure 4-5 Power-Save Control Register (PDCON, offset F0h) . . . . . . . . . . . . . . . . . . . . . 4-7
Figure 5-1 Upper Memory Chip Select Register (UMCS, offset A0h) . . . . . . . . . . . . . . . . . 5-4
Figure 5-2 Low Memory Chip Select Register (LMCS, offset A2h) . . . . . . . . . . . . . . . . . . . 5-6
Figure 5-3 Midrange Memory Chip Select Register (MMCS, offset A6h) . . . . . . . . . . . . . . 5-8
Figure 5-4 PCS
and MCS Auxiliary Register (MPCS, offset A8h). . . . . . . . . . . . . . . . . . . 5-10
Figure 5-5 Peripheral Chip Select Register (PACS, offset A4h) . . . . . . . . . . . . . . . . . . . . 5-12
Figure 6-1 Internal Memory Chip Select Register (IMCS, offset ACh) . . . . . . . . . . . . . . . . 6-3
Figure 7-1 Memory Partition Register (MDRAM, offset E0h). . . . . . . . . . . . . . . . . . . . . . . . 7-1
Figure 7-2 Clock Prescaler Register (CDRAM, offset E2h). . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Figure 7-3 Enable RCU Register (EDRAM, offset E4h) . . . . . . . . . . . . . . . . . . . . . . . . . . . 7-2
Figure 8-1 External Interrupt Acknowledge Bus Cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-8
Figure 8-2 Fully Nested (Direct) Mode Interrupt Controller Connections . . . . . . . . . . . . . 8-10
Figure 8-3 Cascade Mode Interrupt Controller Connections . . . . . . . . . . . . . . . . . . . . . . . 8-11
Figure 8-4 INT0 and INT1 Control Registers (I0CON, I1CON, offsets 38h and 3Ah) . . . . 8-14
Figure 8-5 INT2 and INT3 Control Registers (I2CON, I3CON, offsets 3Ch and 3Eh) . . . . 8-16
Figure 8-6 INT4 Control Register (I4CON, offset 40h) . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-17
Figure 8-7 Timer/DMA Interrupt Control Registers
(TCUCON, DMA0CON, DMA1CON, offsets 32h, 34h, and 36h). . . . . . . . . . . 8-18
Figure 8-8 Watchdog Timer Interrupt Control Register (WDCON, offset 42h). . . . . . . . . . 8-19
Figure 8-9 Serial Port Interrupt Control Register (SPICON, offset 44h) . . . . . . . . . . . . . . 8-20
Figure 8-10 Interrupt Status Register (INTSTS, offset 30h) . . . . . . . . . . . . . . . . . . . . . . . . 8-21
Figure 8-11 Interrupt Request Register (REQST, offset 2Eh) . . . . . . . . . . . . . . . . . . . . . . . 8-22
Figure 8-12 In-Service Register (INSERV, offset 2Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-23
Figure 8-13 Priority Mask Register (PRIMSK, offset 2Ah). . . . . . . . . . . . . . . . . . . . . . . . . . 8-24
Figure 8-14 Interrupt Mask Register (IMASK, offset 28h) . . . . . . . . . . . . . . . . . . . . . . . . . . 8-25
Figure 8-15 Poll Status Register (POLLST, offset 26h) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-26
Figure 8-16 Poll Register (POLL, offset 24h). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-27
Figure 8-17 Example EOI Assembly Code . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28
Figure 8-18 End-of-Interrupt Register (EOI, offset 22h) . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-28
Figure 8-19 Timer and DMA Interrupt Control Registers (T0INTCON, T1INTCON,
T2INTCON, DMA0CON, DMA1CON, offsets 32h, 38h, 3Ah, 34h, and 36h) . . 8-30
Figure 8-20 Interrupt Status Register (INTSTS, offset 30h) . . . . . . . . . . . . . . . . . . . . . . . . 8-31
Figure 8-21 Interrupt Request Register (REQST, offset 2Eh) . . . . . . . . . . . . . . . . . . . . . . . 8-32
Figure 8-22 In-Service Register (INSERV, offset 2Ch) . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8-33
Figure 8-23 Priority Mask Register (PRIMSK, offset 2Ah). . . . . . . . . . . . . . . . . . . . . . . . . . 8-34
Figure 8-24 Interrupt Mask Register (IMASK, offset 28h) . . . . . . . . . . . . . . . . . . . . . . . . . . 8-35