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Peripheral Control Block
4-3
Chapter 13
Chapter 9
Chapter 8
Chapter 12
Offset
(Hexadecimal)
INT2 Control Register
INT1 Control Register
INT0 Control Register
DMA 1 Interrupt Control Register
DMA 0 Interrupt Control Register
Timer Interrupt Control Register
Interrupt Status Register
Interrupt Request Register
In-service Register
Priority Mask Register
Interrupt Mask Register
Poll Status Register
Poll Register
End-of-Interrupt Register
Interrupt Vector Register
10
12
Synchronous Serial Transmit 1 Register
14
16
18
3E
40
42
PIO Mode 0 Register
70
72
74
Register Name
ww
ww
ww
Changed from 80C186
microcontroller.
44
76
78
7A
5C
5E
60
62
66
50
52
54
56
58
5A
Timer 2 Mode/Control Register
Timer 2 Maxcount Compare A Register
Timer 2 Count Register
Timer 1 Mode/Control Register
Timer 1 Maxcount Compare B Register
Timer 1 Maxcount Compare A Register
Timer 1 Count Register
Timer 0 Mode/Control Register
Timer 0 Maxcount Compare B Register
Timer 0 Maxcount Compare A Register
Timer 0 Count Register
INT3 Control Register
3C
3A
38
36
34
32
30
2E
2C
2A
28
26
24
22
20
PIO Data 1 Register
PIO Direction 1 Register
PIO Mode 1 Register
PIO Data 0 Register
PIO Direction 0 Register
Serial Port Interrupt Control Register
Watchdog Timer Control Register
INT4 Control Register
Synchronous Serial Receive Register
Synchronous Serial Transmit 0 Register
Synchronous Serial Enable Register
Synchronous Serial Status Register
Notes:
Gaps in offset addresses indicate reserved registers.