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Index I-7
Processor Status Flags Register (FLAGS), 2-2
Product support
bulletin board service, iii
documentation and literature, iii
technical support hotline, iii
PSE bit (PSRAM Mode Enable), 5-7
Pseudo Static RAM (PSRAM) support, 3-21
Pullup/pulldown resistor, 13-3
Q
Quad word data type, 2-8
R
R19-R8 field (Relocation Address Bits), 4-4
R1-R0 field (Wait State Value)
Low Memory Chip Select Register, 5-7
Midrange Memory Chip Select Register, 5-9
PCS and MCS Auxiliary Register, 5-11
Peripheral Chip Select Register, 5-13
Upper Memory Chip Select Register, 5-5
R2 bit (Ready Mode)
Low Memory Chip Select Register, 5-7
Midrange Memory Chip Select Register, 5-9
PCS and MCS Auxiliary Register, 5-11
Peripheral Chip Select Register, 5-13
Upper Memory Chip Select Register, 5-5
R3 bit (Wait-State Value)
Peripheral Chip Select Register, 5-13
RC field (Reset Configuration), 4-5
RC8-RC0 field (Refresh Counter Reload Value), 7-2
RD signal (Read Strobe), 3-12
RDATA field (Receive Data), 11-6
RDR bit (Receive Data Ready), 11-4
RE field (Internal RAM Enable)
Internal Memory Chip Select Register, 6-3
RE/TE bit (Receive/Transmit Error Detect), 12-3
Read and write bus timing, 3-19–3-20
Ready signal programming, 5-2
Register Indirect mode addressing, 2-10
Register operands, 2-10
Register set
base and index registers, 2-1
general registers, 2-1
segment registers, 2-1
stack pointer register, 2-1
status and control registers, 2-1
Registers
Clock Prescaler (CDRAM, Offset E2h), 7-2
DMA 0 Control (D0CON, Offset CAh), 10-3
DMA 0 Interrupt Control (DMA0CON, Offset 34h), 8-
18, 8-30
DMA 0 Source Address High (D0SRCH, Offset
C2h), 10-8
DMA 0 Source Address Low (D0SRCL, Offset C0h),
10-9
DMA 0 Transfer Count (D0TC, Offset C8h), 10-5
DMA 1 Control (D1CON, Offset DAh), 10-3
DMA 1 Destination Address High (D0DSTH, Offset
C6h), 10-6
DMA 1 Destination Address High (D1DSTH, Offset
D6h), 10-6
DMA 1 Destination Address Low (D0DSTL, Offset
C4h), 10-7
DMA 1 Destination Address Low (D1DSTL, Offset
D4h), 10-7
DMA 1 Interrupt Control (DMA1CON, Offset 36h), 8-
18, 8-30
DMA 1 Source Address High (D1SRCH, Offset
D2h), 10-8
DMA 1 Source Address Low (D1SRCL, Offset D0h),
10-9
DMA 1 Transfer Count (D1TC, Offset D8h), 10-5
Enable RCU (EDRAM, Offset E4h), 7-2
End-of-Interrupt (EOI, Offset 22h), 8-28
In-Service (INSERV, Offset 2Ch), 8-23, 8-33
INT0 Control (I0CON, Offset 38h)
Master mode, 8-14
INT1 Control (I1CON, Offset 3Ah)
Master mode, 8-14
INT2 Control (I2CON, Offset 3Ch)
Master mode, 8-16
INT3 Control (I3CON, Offset 3Eh)
Master mode, 8-16
INT4 Control (I4CON, Offset 40h)
Master mode, 8-17
Internal Memory Chip Select (IMCS, Offset ACh), 6-
3
Interrupt Mask (IMASK, Offset 28h), 8-25, 8-35
Interrupt Request (REQST, Offset 2Eh), 8-22, 8-32
Interrupt Status (INSTS, Offset 30h), 8-21
Interrupt Status (INTSTS, Offset 30h), 8-31
Interrupt Vector (INTVEC, Offset 20h), 8-37
Low Memory Chip Select (LMCS, Offset A2h), 5-6
Memory Partition (MDRAM, Offset E0h), 7-1
Midrange Memory Chip Select (MMCS, Offset A6h),
5-8
PCS and MCS Auxiliary (MPCS, Offset A8h), 5-10
Peripheral Chip Select (PACS, Offset A4h), 5-12
Peripheral Control Block Relocation (RELREG,
Offset FEh), 4-4
PIO Data 0 (PDATA0, Offset 74h), 13-5
PIO Data 1 (PDATA1, Offset 7Ah), 13-5
PIO Direction 0 (PDIR0, Offset 72h), 13-4
PIO Direction 1 (PDIR1, Offset 78h), 13-4
PIO Mode 0 (PIOMODE0, Offset 70h), 13-3
PIO Mode 1 (PIOMODE1, Offset 76h), 13-3
Poll (POLL, Offset 24h), 8-27
Poll Status (POLLST, Offset 26h), 8-26