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DMA Controller
10-7
10.3.4 DMA Destination Address Low Register
(Low Order Bits) (D0DSTL, Offset C4h, D1DSTL, Offset D4h)
Figure 10-5 shows the DMA Destination Address Low register. The sixteen bits of this
register are combined with the four bits of the DMA Destination Address High register (see
Figure 10-4) to produce a 20-bit destination address.
Figure 10-5 DMA Destination Address Low Register (D0DSTL, D1DSTL, offsets C4h and D4h)
The value of D0DSTL and D1DSTL at reset is undefined.
Bits 15–0: DMA Destination Address Low (DDA15–DDA0)—These bits are driven onto
A15–A0 during the write phase of a DMA transfer.
15
70
DDA15–DDA0