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I-4 Index
DMA 1 Destination Address High Register, 10-6
DMA 1 Destination Address Low Register, 10-7
DMA 1 Interrupt Control Register
Master mode, 8-18
Slave mode, 8-30
DMA 1 Source Address High Register, 10-8
DMA 1 Source Address Low Register, 10-9
DMA 1 Transfer Count Register, 10-5
Documentation, iii, xiv
Double word data type, 2-8
DR/DT bit (Data Receive/Transmit Complete), 12-3
DRQ1-DRQ0 signals (DMA Requests), 3-4
DSA15-DSA0 field (DMA Source Address Low), 10-9
DSA19-DSA16 field (DMA Source Address High), 10-8
DT/R signal (Data Transmit or Receive), 3-4
E
E bit (Enable RCU), 7-2
Effective address, 2-10
Emulators, pins used by, 3-17
EN bit (Enable Bit)
Timer 0 Mode/Control Register, 9-3
Timer 1 Mode/Control Register, 9-3
Timer 2 Mode/Control Register, 9-5
EN bit (Enable Power-Save Mode), 4-7
Enable RCU Register, 7-2
End-of-Interrupt (EOI) Register
description, 8-28
End-of-interrupt (EOI) Register
programming, 8-12
EX bit (Pin Selector), 5-11
Example system design, 1-6–1-7
Exceptions, instruction, 8-3
EXT bit (External Clock Bit)
Timer 0 Mode/Control Register, 9-4
Timer 1 Mode/Control Register, 9-4
External clock source, 3-24
External interrupt acknowledge bus cycles table, 8-8
Extra Segment (ES) Register, 2-8
F
F2-F0 field (Clock Divisor Select)
System Configuration Register, 4-8
FER bit (Framing Error), 11-4
Figure
DMA Unit Block Diagram, 10-2
external interrupt acknowledge bus cycles, 8-8
Fully nested mode interrupt controller connections,
8-10
Read and write bus timing, 3-19–3-20
FLAGS Register, 2-2
Frequency, clock, 3-23
FTP site, xiv
Fully nested mode, 8-10
Fully nested mode interrupt controller connections, 8-10
Functional system design, 1-6–1-7
FusionE86 catalog, xiv
G
General registers, 2-1
H
HLDA signal (Bus Hold Acknowledge), 3-4
HOLD signal (Bus Hold Request), 3-5
I
I/O space, 2-4
I4-I0 field (Interrupt In-Service), 8-23
I4-I0 field (Interrupt Mask), 8-25
I4-I0 field (Interrupt Requests), 8-22
IF bit (Interrupt-Enable Flag)
Processor Status Flags Register, 2-3
IF bit (Interrupt-Enable flag)
programming, 8-2
IMDIS signal (Internal Memory Disable), 3-13
Immediate operands, 2-10
Indexed mode addressing, 2-10
INH bit (Inhibit Bit)
Timer 0 Mode/Control Register, 9-3
Timer 1 Mode/Control Register, 9-3
Timer 2 Mode/Control Register, 9-5
In-Service Register
Master mode, 8-23
Slave mode, 8-33
Instruction exceptions, 8-3
Instruction set, 2-4
INT bit (Interrupt Bit)
Timer 0 Mode/Control Register, 9-3
Timer 1 Mode/Control Register, 9-3
Timer 2 Mode/Control Register, 9-5
INT0 Control Register
Master mode, 8-14
INT0 signal (Maskable Interrupt Request 0), 3-5
INT1 Control Register
Master mode, 8-14
INT1 signal (Maskable Interrupt Request 1), 3-5
INT2 Control Register