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Timer Control Unit
9-7
9.2.5 Timer Maxcount Compare Registers
(T0CMPA, Offset 52h, T0CMPB, Offset 54h, T1CMPA, Offset 5Ah,
T1CMPB, Offset 5Ch, T2CMPA, Offset 62h)
These registers serve as comparators for their associated count registers. Timer 0 and
timer 1 each have two maximum count compare registers. See Figure 9-4.
Timer 0 and timer 1 can be configured to count and compare to register A and then count
and compare to register B. Using this method, the TMROUT0 or TMROUT1 signals can
be used to generate waveforms of various duty cycles.
Timer 2 has one compare register, T2CMPA.
If a maximum count compare register is set to 0000h, the timer associated with that compare
register will count from 0000h to FFFFh before requesting an interrupt. With a 40-MHz
clock, a timer configured this way interrupts every 6.5536 ms.
Figure 9-4 Timer Maxcount Compare Registers
(T0CMPA, T0CMPB, T1CMPA, T1CMPB, T2CMPA,
offsets 52h, 54h, 5Ah, 5Ch, and 62h)
The value of these registers at reset is undefined.
Bits 15–0: Timer Compare Value (TC15–TC0)—This register contains the maximum
value a timer will count to before resetting its count register to 0.
15
70
TC15–TC0